Journal of Electrical and Computer Engineering / 2018 / Article / Fig 14

Research Article

Improved Design of Bit Synchronization Clock Extraction in Digital Communication System

Figure 14

System simulated results with adding digital filter. CLK_LOCAL: the local clock, INSIGNAL: the input signal, Syn_Clock: the synchronization clock, DF_Deduct: the leading control pulse of digital filter module, DF_Add: the lagging control pulse of digital filter module, Before_Dvf: control module output/frequency divider input.