As the density of VLSI design increases, more processors or cores can be placed on a single chip. Therefore, the design of a multiprocessor system-on-Chip (MP-SoC) architecture, which demands high throughput, low latency, and reliable global communication services, cannot be done by just using current bus-based on-chip communication infrastructure. Network on Chip (NoC) has been proposed in recent years as a promising solution of on-chip communication network to provide better scalability, performance, and modularity for current MP-SoC architectures.

The goal of this special issue is to bring together academic research and industry experiences focused on architectures, design methodologies, and case studies for networks on chips. Potential topics include, but are not limited to:

• Architectures
  • On-chip, multi-chip, and cluster interconnection networks
  • Dynamic on-chip network reconfiguration
  • Router microarchitecture
  • NoC physical link design
  • Low-power and fault-tolerant NoC
  • 3D on-chip architectures, emerging technologies, and new design paradigms
• Design methodologies
  • Switching, buffering, and routing algorithms
  • Flow control and congestion management
  • Design space exploration and tradeoff analysis
  • NoC testing and verification
• Case studies
  • Research MP-SoC prototypes using on-chip networks
  • Industrial experiences on MP-SoCs using on-chip networks

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/jece/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable: