Journal of Electrical and Computer Engineering

Networks-on-Chip: Architectures, Design Methodologies, and Case Studies


Publishing date
15 Mar 2012
Status
Published
Submission deadline
15 Sep 2011

Lead Editor

1Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign; and Department of Electrical Engineering, National Taiwan University, Taiwan

2Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan

3Electronic and Computer Engineering Department, Hong Kong University of Science and Technology, Hong Kong, China


Networks-on-Chip: Architectures, Design Methodologies, and Case Studies

Description

As the density of VLSI design increases, more processors or cores can be placed on a single chip. Therefore, the design of a multiprocessor system-on-Chip (MP-SoC) architecture, which demands high throughput, low latency, and reliable global communication services, cannot be done by just using current bus-based on-chip communication infrastructure. Network on Chip (NoC) has been proposed in recent years as a promising solution of on-chip communication network to provide better scalability, performance, and modularity for current MP-SoC architectures.

The goal of this special issue is to bring together academic research and industry experiences focused on architectures, design methodologies, and case studies for networks on chips. Potential topics include, but are not limited to:

  • Architectures
    • On-chip, multi-chip, and cluster interconnection networks
    • Dynamic on-chip network reconfiguration
    • Router microarchitecture
    • NoC physical link design
    • Low-power and fault-tolerant NoC
    • 3D on-chip architectures, emerging technologies, and new design paradigms
  • Design methodologies
    • Switching, buffering, and routing algorithms
    • Flow control and congestion management
    • Design space exploration and tradeoff analysis
    • NoC testing and verification
  • Case studies
    • Research MP-SoC prototypes using on-chip networks
    • Industrial experiences on MP-SoCs using on-chip networks

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/jece/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:


Articles

  • Special Issue
  • - Volume 2012
  • - Article ID 634930
  • - Editorial

Networks-on-Chip: Architectures, Design Methodologies, and Case Studies

Sao-Jie Chen | An-Yeu Andy Wu | Jiang Xu
  • Special Issue
  • - Volume 2012
  • - Article ID 107821
  • - Research Article

Intelligent On/Off Dynamic Link Management for On-Chip Networks

Andreas G. Savva | Theocharis Theocharides | Vassos Soteriou
  • Special Issue
  • - Volume 2012
  • - Article ID 537286
  • - Research Article

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands

Anish S. Kumar | M. Pawan Kumar | ... | Giovanni De Micheli
  • Special Issue
  • - Volume 2012
  • - Article ID 728191
  • - Research Article

Status Data and Communication Aspects in Dynamically Clustered Network-on-Chip Monitoring

Ville Rantala | Pasi Liljeberg | Juha Plosila
  • Special Issue
  • - Volume 2012
  • - Article ID 278735
  • - Research Article

A Hardware Design of Neuromolecular Network with Enhanced Evolvability: A Bioinspired Approach

Yo-Hsien Lin | Jong-Chen Chen
  • Special Issue
  • - Volume 2012
  • - Article ID 509465
  • - Review Article

Networks on Chips: Structure and Design Methodologies

Wen-Chung Tsai | Ying-Cherng Lan | ... | Sao-Jie Chen
  • Special Issue
  • - Volume 2012
  • - Article ID 697039
  • - Research Article

Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks

Po-Tsang Huang | Wei Hwang
Journal of Electrical and Computer Engineering
 Journal metrics
Acceptance rate17%
Submission to final decision90 days
Acceptance to publication37 days
CiteScore2.900
Impact Factor-
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