Journal of Electrical and Computer Engineering

Hardware Implementation of Digital Signal Processing Algorithms


Publishing date
26 Apr 2013
Status
Published
Submission deadline
07 Dec 2012

Lead Editor

1Department of Electrical and Computer Engineering, San Diego State University, 5500 Campanile Drive, San Diego, CA 92182-1309, USA

2Department of Biomedical, Electronic and Telecommunication Engineering, University of Naples Federico II, Via Claudio 21, 80125 Naples, Italy

3Division of Electronics Systems, Department of Electrical Engineering, Linköping University, 581 83 Linköping, Sweden


Hardware Implementation of Digital Signal Processing Algorithms

Description

As the technology advances, more complicated systems emerge, requiring sophisticated algorithms often encompassing very complex digital signal processing (DSP) techniques. Although the performance of programmable processors is continuously improving, hardware implementation of DSP algorithms is increasingly required in several areas such as wireless communications, multimedia systems, computer networks, and biomedicine. There are several challenges that engineers face while designing hardware DSP algorithms. These challenges are heightened by the needs of huge computing power (required in real-time systems), reducing energy consumption (for portable, battery-operated systems) and reducing costs. Technology scaling adds additional difficulties related to variability of device parameters, leakage currents, and signal integrity. Therefore, hardware implementation of DSP algorithms has gained much attention during past years and is the focus of this special issue. Original manuscripts are welcomed in this special issue. Potential topics include, but are not limited to:

  • FPGA and ASIC implementations of DSP algorithms
  • VLSI building blocks for hardware implementation of DSP algorithms
  • Low-power hardware realization of DSP algorithms
  • DSP hardware for sensor systems
  • Implementation of DSP algorithm in System-on-Chip (SoC)
  • High-level synthesis for hardware implementation of DSP algorithms
  • Hardware implementation of DSP algorithms for wireless communications
  • Hardware implementation of DSP algorithms for biomedical signal processing
  • Hardware implementation of DSP algorithms for image, video, and multimedia processing
  • Hardware implementation of DSP algorithms for machine learning
  • Hardware implementation of DSP algorithms for audio speech and language processing

Before submission authors should carefully read over the journal's Author Guidelines, which are located at http://www.hindawi.com/journals/jece/guidelines/. Prospective authors should submit an electronic copy of their complete manuscript through the journal Manuscript Tracking System at http://mts.hindawi.com/ according to the following timetable:


Articles

  • Special Issue
  • - Volume 2013
  • - Article ID 782575
  • - Editorial

Hardware Implementation of Digital Signal Processing Algorithms

Ashkan Ashrafi | Antonio G. M. Strollo | Oscar Gustafsson
  • Special Issue
  • - Volume 2013
  • - Article ID 240814
  • - Research Article

Efficient Parallel Carrier Recovery for Ultrahigh Speed Coherent QAM Receivers with Application to Optical Channels

Pablo Gianni | Laura Ferster | ... | Mario R. Hueda
  • Special Issue
  • - Volume 2013
  • - Article ID 587108
  • - Research Article

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Ariel L. Pola | Juan E. Cousseau | ... | Mario R. Hueda
  • Special Issue
  • - Volume 2013
  • - Article ID 741251
  • - Research Article

Holistic Biquadratic IIR Filter Design for Communication Systems Using Differential Evolution

Alexander Melzer | Andreas Pedross | Manfred Mücke
  • Special Issue
  • - Volume 2013
  • - Article ID 834793
  • - Research Article

Asynchronous Realization of Algebraic Integer-Based 2D DCT Using Achronix Speedster SPD60 FPGA

Nilanka Rajapaksha | Amila Edirisuriya | ... | Vassil S. Dimitrov
  • Special Issue
  • - Volume 2013
  • - Article ID 129589
  • - Research Article

FPGA Implementation of Gaussian Mixture Model Algorithm for 47 fps Segmentation of 1080p Video

Mariangela Genovese | Ettore Napoli | ... | Antonio G. M. Strollo
Journal of Electrical and Computer Engineering
 Journal metrics
Acceptance rate17%
Submission to final decision101 days
Acceptance to publication44 days
CiteScore0.690
Impact Factor-
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