Modeling and Simulation of Special Shaped SOI Materials for the Nanodevices Implementation

Abstract

In the industrial chain of the nanomaterials for electronic devices, a main stage is represented by the wafer characterization. This paper is starting from a standard SOI wafer with 200 nm film thickness and is proposing two directions for the SOI materials miniaturization, indexing the static characteristics by simulation. The first SOI nanomaterial is a sub-10 nm Si-film with a rectangular shape. The influence of the buried interface fixed charges has to be approached by the distribution theory. The second proposal studies the influence of the vacuum cavity in a “U” shaped SOI nanofilm. In all cases, with rectangular or “U” shape film, the simulations reveal transfer characteristics with a maximum and output characteristics with a minimum for sub-10 nm thickness of the SOI film.

1. Introduction

The modeling of the classical devices [1] or novel nanodevices [2] improves the design and explains some phenomena experimentally encountered [3].

In the SOI structures, two oxide-semiconductor interfaces exist with specific associated charges. Conventional models ignore the charges situated at the buried oxide-substrate interface, being focused just on the front and back channels conduction in the silicon film. All these fixed charges, expressed in electrons per cm², are physically spread into a small volume that becomes significant in ultra-thin films. This paper presents a suitable model for the flat-band voltage, based on the δ-distribution strings, which include this bottom interface. Hence, the model accuracy increases in the SOI nanofilms materials, accordingly with our theory and numerical simulations. The electrons confinement effect is continuing to be studied in “U” shape SOI films. Whether the conduction channel occurs at the film bottom, the upper part of the SOI film was removed, monitoring the static characteristics of some SOI-MOSFETs.

This paper proposes two directions for the electrical characterization of the nano-SOI (silicon on insulator) materials, by simulation of the electrical characteristics of some devices. The first class of the studied SOI transistors has a rectangular film shape. In this case, the effect of the buried interface fixed charges is modeled with the distribution theory [4, 5].

The classical HTA SIMOX (high temperature annealing separation by implanted oxygen), technology offers SOI wafers with 200 nm Si-film on 400 nm BOX with fixed charges in the range 𝑄_ox=10¹⁰÷10¹²e/cm², [6]. This charge is located in a shallow oxide slice. An SOI device has the interfaces: 𝐼₁-Si-film/BOX, 𝐼₂-BOX/Substrate, and eventually the upper interface 𝐼₀-gate oxide/Si-film; see Figure 1. The classical model strongly insists on the electric charges from 𝐼₀ and 𝐼₁ interfaces, [7]. In fact, all these fixed charges are physically spread into a small volume. In ultra-thin oxide structures, this kind of charge must be modeled as a bulk charge density [8].

Figure 1 

The current flow in a cross-section of a rectangular SOI-MOSFET, with SOI film thickness less than 200 nm.

This paper emphasizes that the effect of a fixed charges about 10¹² e/cm², at the bottom interface 𝐼₂ could be neglected in a classical SOI-MOSFET with 200 nm Si/400 nm BOX sizes, while it is the main charge in a nano-SOI-MOSFET with 10 nm × 10 nm × 10 nm Si/10 nm × 10 nm × 10 nm BOX.

Transforming 10¹²e/cm² in 10⁻² e/nm²= 1 electron per 10 nm × 10 nm that means that the back interface 𝐼₂ (Si/BOX) is charged with one indivisible elementary charge. A model with a discontinuous function escapes from the integration operation. Just the Dirac distribution can correctly describe it as a bulk charge density.

Beside to the strong effect of the buried interface charge on the current through a SOI nanotransistor, the current confinement is modulated by the shape of the SOI material, in sub-10 nm Si-film devices, [9]. The influence of the vacuum cavity on the static characteristics, in a “U” shape nanotransistor, was the second direction of study for this paper; see Figure 2.

Figure 2 

The conceptual architecture of the nanotransistor with a cavity, with SOI film thickness less than 10 nm.

The notations from Figures 1 and 2 are 𝑡_n+: the Si-n⁺ region thickness, 𝑡_f: the Si-p film thickness, 𝑡_BOX: the buried oxide (BOX) thickness, 𝑡_Sb: the Si-substrate thickness, 𝑙_n+: the Si-n⁺ region length, 𝑙_C: the cavity length, and 𝑊_n+: the Si-n⁺ region width.

The joint of both subjects will be finally motivated by similar output characteristics with minimum and transfer characteristics with maximum, both for rectangular shape sub-10 nm or “U” shaped SOI films.

2. The Analytical Model with Distributions

Firstly, the characterization of the back interface of a nano-SOI-MOSFET, using the pseudo-MOS transistor technique [10], will be presented. This is a dedicated transistor for the in situ electrical characterization, working like an upside down SOI-MOSFET controlled by the back gate, [11]. All unprocessed SOI wafers contain a pseudo-MOS transistor with two metals in contact with the semiconductor layer, as source and drain. The substrate acts like the gate contact in a classical SOI-MOSFET, Figure 1. One key parameter that contains information about the back interface charge is the flat band voltage, 𝑉_FB, [12]. This parameter is extracted from the measured 𝐼_D-𝑉_GS curves or directly from simulations with its definition.

In order to be focused just on the fixed interface charge density, others effects like interface traps, mobile ionic charge and metal semiconductor work function are neglected in the analytical model and in simulations.

The SOI structure associated with the pseudo-MOS transistor is modeled. Identical doping concentrations in film and substrate, 𝑁_𝐴, are considered to avoid the film-substrate work function in the flat-band voltage expression.

The source and drain are grounded, while the gate is biased at 𝑉_FB voltage, Figure 3(a). By Poisson’s equation integration, the flat-band voltage 𝑉_FBC is computed by the classical method [13]𝑉_FBC𝑄=−^𝐼1𝜀_ox⋅𝑡_BOX−𝑄_𝐼1+𝑄_𝐼2²2𝜀_Si𝑞𝑁_𝐴, (1) where 𝑡_BOX is the buried oxide thickness, 𝜀_Si, 𝜀_ox, respectively, are the dielectric permittivity of silicon and oxide, 𝑉_FBC is the classical flat-band voltage given by the condition of the potential zeroing in the entire SOI film. The depleted film thickness 𝑡_df→ 0 for 𝑉_G→𝑉_FB, 𝑄_𝐼1, 𝑄_𝐼2 are, respectively, the sheet charge densities from the upper and buried interface and the last term, 𝑉_FB-Sb models the substrate depletion on distance 𝑡_ds in Figures 3(a) and 3(b) presents the interface charges scattered into smalls volumes, as a real situation, both in micro- or nano-SOI structures. Hence, a relationship between surface charge density 𝑄_𝐼 and the bulk electric charge density 𝑞_𝑉 for whatever 𝐼₁ or 𝐼₂ interface is 𝑄_𝐼=lim_Δ𝑡→00^Δ𝑡𝑞_𝑉⋅𝑑𝑡=lim_Δ𝑡→0𝑞_𝑉⋅Δ𝑡, (2) where Δt is interpreted as a spreading coefficient. The surface charge 𝑄_𝐼 was spread into an infinitesimal volume: Δt·𝑆, with Δt→0 and 𝑞_𝑉 = ct, 𝑆 being the area. If 𝑞_𝑉 is modeled with a function like this𝑞_𝑉=𝑞_𝑆,expressedine/cm³{0},,for𝑡=0,0,for𝑡∈ℜ− (3) where 𝑞_𝑆 is a real number associated with 𝑄_𝐼/Δt. Then, 𝑄_𝐼 becomes zero, accordingly with (2), escaping from the integration operation. In order to obtain 𝑄_𝐼 finite in (2), 𝑞_𝑉 must tend to ∞, considering Δ𝑡→0. But this is a δ distribution. On the horizontal axis Ot, along the SOI structure from Figure 2(a), the bulk charge density can be written with the Dirac distribution𝑞_𝑉(𝑡)=𝑄_𝐼1⋅𝛿₀(𝑡)+𝑄_𝐼2⋅𝛿_𝑡BOX(𝑡). (4)

(a)

(b)

Figure 3 

A segment of SOI structure with localization of interface charges (a) with 𝑄𝐼1, 𝑄𝐼2 as sheet charge density and (b) with 𝑄𝐼1, 𝑄𝐼2 scattered onto the Δ𝑡1,Δ𝑡2 thicknesses.

The electric field distribution is expressed as a Heaviside distribution after the first integration. The potential imposes a second integration that is difficult in distribution terms. Due to this reason, is preferred a model based on δ-generator strings. The functional analysis demonstrated that Dirac distribution is the limit of the following string of regulates distribution, pulse-type [14]𝐷_𝑡𝑖(𝑡)=1Δ𝑡_𝑖,for𝑡∈𝑡_𝑖,𝑡_𝑖+Δ𝑡_𝑖,0,for𝑡∉𝑡_𝑖,𝑡_𝑖+Δ𝑡_𝑖, (5) where t_i is the spatial coordinate for 𝑄_𝐼𝑖, i = 1 or 2 and Δ𝑡𝑖→0 (∀i) represent the spreading coefficients for 𝑄_𝐼1, 𝑄_𝐼2; see Figure 2(b). Now, the bulk electric charge distribution can be written with δ-generators string𝑞_𝑉(𝑡)=𝑄_I1⋅𝐷₀(𝑡)+𝑄_I2⋅𝐷_𝑡BOX(𝑡). (6) The string D_ti (t) has the advantage of being an integrable function. The integral ∫^∞_−∞𝐷_𝑡𝑖(𝑡)𝑑𝑡 gives 1 like δ distribution. The convergence toward δ-distribution is successfully fulfilled for Δ𝑡_𝑖→0. In the old SOI technologies, Δ𝑡_𝑖 = 20 nm = 2·10⁻⁸ m [15], but in the ultimate stage of nanotechnologies, Δ𝑡_𝑖 could reach the atomic sizes— Δ𝑡_𝑖≈ 0.3 nm = 3·10⁻¹⁰ m, closer to zero, [16]. Hence, our model is more accurate for nanodevices. After two integration operations of the Poisson’s equation, the following potential drops result:For𝑡∈−𝑡_f,0⟶Φ_film=0,For𝑡∈0,Δ𝑡₁⟶Φ_Δ𝑡1𝑄=−^𝐼12𝜀_ox⋅Δ𝑡₁,For𝑡∈Δ𝑡₁,𝑡_BOX−Δ𝑡₂⟶Φ_BOX𝑄=−^𝐼1𝜀_ox⋅𝑡_BOX−Δ𝑡₁−Δ𝑡₂,For𝑡∈𝑡_BOX−Δ𝑡₂,𝑡_BOX⟶Φ_Δ𝑡2𝑄=−^𝐼1𝜀_ox⋅Δ𝑡₂−𝑄_𝐼22𝜀_ox⋅Δ𝑡₂. (7) Adding the previous voltages, Φ_film, Φ_BOX, Φ_Δ𝑡1, Φ_Δ𝑡2—the potentials drops, respectively, over film, neutral oxide, and Δ𝑡₁ and Δ𝑡₂ regions from the buried oxide, with the potential drop over the depleted substrate, 𝑉_FB-Sb, the complete flat-band voltage expression with distribution terms, 𝑉_FBC, is𝑉_FBD𝑄=−^𝐼1𝜀_ox⋅𝑡_BOX−Δ𝑡₁2−𝑄_𝐼22𝜀_ox⋅Δ𝑡₂−𝑄_𝐼1+𝑄_𝐼2²2𝜀_Si⋅𝑞𝑁_𝐴. (8)

If the spreading coefficients are approximated with zero (Δ𝑡_1,2 = 0), the new model (8) becomes the conventional model (1). The validity of the new model (8) will be discussed in the next paragraph, in comparison with classical model (1).

3. The Simulation Results for the SOI Structure with 200 nm Thickness

In this paragraph, the previous models (1) and (8) are tested using Atlas simulations of a pseudo-MOS transistor integrated on a SOI wafer with 200 nm Si-p-film and 400 nm buried oxide. The constructive data were [17]: 𝑡_n+ = 0.2 μm, 𝑡_BOX = 0.4 μm, 𝑡_Sb = 1 μm, the doping concentrations in film and substrate is 𝑁_𝐴 = 2 × 10¹⁵ cm⁻³.

The applied voltages were 𝑉_D = 0 V⋯ + 4 V, 𝑉_S = 0 V and 𝑉_G = 0 V⋯ − 3 V in order to estimate the simulated flat-band voltage that must be applied on gate.

Figure 4(a) presents the potential distribution and the holes concentration in an intermediate situation at 𝑉_G = −1.8 V, through the structure with 200 nm Si-film thickness. A negative gate bias induces a holes crowding in the p-type film. Near drain, where 𝑉_GD is higher than 𝑉_GS, the holes reached 𝑝=8×10¹⁵ cm⁻³ and near source 𝑝=4×10¹⁵ cm⁻³ > 2 ×10¹⁵ cm⁻³ = 𝑁_𝐴, Figure 4(b). From the longitudinal holes distribution can be observed the holes concentration decreasing in the substrate; see Figure 4(c). This simulation proves the substrate depletion effect.

(a)

(b)

(c)

Figure 4 

(a) The potential distribution in the 200 nm SOI structure; (b) the holes concentration across the structure; (c) the holes concentration along the structure.

Figure 5 presents the electron concentration in the same structure with 200 nm film thickness. A positive gate bias induces an electron inversion channel in p-type film (e.g., 𝑛|_{𝑦=0.2𝑢m}=10¹⁶cm⁻³> 5·10¹⁵ cm⁻³ = 𝑁_𝐴-film); see Figure 5.

(a)

(b)

Figure 5 

Detail in film for the electron concentration rised for a positive gate voltage.

Atlas takes into account the interface electric charge by the statements Interface𝑦_min=0.1𝑦_max=0.5,QF=5𝑒10,Interface𝑦_min=0.5𝑦_max=0.8,QF=1𝑒12. (9)

The metal semiconductor work function was zero for the source, drain, and gate contacts, defined as “neutral”. The simulated flat-band voltage value, 𝑉_FBS was searched accordingly with the theoretical definition. For 𝑉_S = 0 V, the 𝑉_G voltage was searched so that the potential in the film bottom becomes zero.

Figure 6 presents the potential distribution between source and gate, after Atlas running. Initially, the potential distribution was extracted for 𝑉_GS = 0 V in order to observe the potential bending in the absence of some external electrical voltages due to the interface charges densities 𝑄_𝐼1 and 𝑄_𝐼2. In this case, the potential at the film bottom reaches +0.28 V at 𝑥 = 0.2 μm; see Figure 6. Then, the gate voltage was increased so that the potential at the coordinate 𝑥 = 0.2 μm decreases to 0 V. This occurs for 𝑉_GS = −1.95 V in Figure 6 consequently; 𝑉_FBS = −1.95 V.

Figure 6 

The potential distribution in the 200 nm structure between source and gate.

On the other hand, the classical model (1) provides a fix value 𝑉_FBC = −1.77 V and the new model (8) based on the distribution generation strings gives 𝑉_FBD = −1.93 V, fitting the spreading coefficients to Δ𝑡₁ = 0.5 nm and Δ𝑡₂ = 7 nm.

All these results are briefly shown in Figure 7, where the old model (1) gives 9.3% error, while the new model (8) can adjust the error to 1.03%.

Figure 7 

The flat-band voltages: 𝑉FBS = −1.95 V, 𝑉FBC = −1.77 V, and 𝑉FBD= −1.93 V, besides to the relative errors for 𝑉FBC, 𝑉FBD in respect with 𝑉FBS.

A comparison of the simulated parameter 𝑉_FBS with a measured flat-band voltage, 𝑉_FBM, is possible, monitoring the transfer characteristics of the pseudo-MOS transistor made on the SOI wafer with 200 nm Si-p-film and 400 nm buried oxide, [17]. In order to extract the flat-band voltage, the source was grounded, while the drain was maintained at +0.3 V, and the gate voltage was varied from −5 V up to +5 V in order to induce the flat-band conditions in the device. From the transfer characteristics, the measured flat-band voltage results: 𝑉_FBM = −2.16 V for p-type film and +4.25 V for n-type film, [17, 18]. In our case, the closest values to the experimental parameter, 𝑉_FBM = −2.16 V, are the simulated and distribution model: 𝑉_FBS = −1.95 V and 𝑉_FBD = −1.93 V. Obviously, the classical model (1), 𝑉_FBC = −1.77 V, loses the accuracy, neglecting the buried oxide interface. However, the discrepancy among experiments, simulations, and analytical values is still small at 200 nm film thickness and is predictable to becomes consistent for sub-20 nm films.

4. Simulation Results for Sub-10 nm Rectangular SOI Structures with Interface Charges

The investigation of the nano-SOI-MOSFETs is continuing with the downscale of the film thicknesses: for Si-film from 200 nm to 50 nm, 10 nm, and 2 nm and for BOX layer from 400 nm to 50 nm, 10 nm, and 4 nm. The doping concentrations are 𝑁_𝐴=5×10¹⁵ cm⁻³ both in film and substrate. The interface electric charge densities are 𝑄_𝐼1=5×10¹⁵ e/cm² and 𝑄_𝐼2 = 10¹² e/cm².

The simulated transfer characteristics show the evolution of the 𝐼_D-𝑉_GS curves from: (a) 50 nm, (b) 10 nm, (c) 2 nm thickness of the semiconductor SOI film; see Figure 8. The typical characteristic shape of a standard SOI-MOSFET is fulfilled till 10 nm. From these curves, the simulated flat-band voltage can be extracted, as the voltage that opens the accumulation channel and produces the current increases: 𝑉_FBS = −0.9 V for 50 nm structure and 𝑉_FBS = −0.8 V for 10 nm structure. Under this value, an 𝐼_D-𝑉_GS curve with a maximum occurs, probably due to the electrons confinement effect. The simulated flat-band voltage cannot be still extracted from the 𝐼_D-𝑉_GS curve.

(a)

(b)

(c)

Figure 8 

The 𝐼D-𝑉GS characteristics for (a) 50 nm (b) 10 nm and (c) 2 nm thickness of the semiconductor SOI film.

In order to check these assessments, the output characteristics are also investigated, to observe the typical effect of transistor. Figure 8 comparatively presents the 𝐼_D-𝑉_DS curves for different semiconductor SOI thickness: 10 nm and 2 nm. The typical shape with saturation occurs till 10 nm film thickness. For sub-10 nm the characteristics takes atypical shape with minimum, Figure 8 for 𝑡_f = 2 nm.

A comparison among the simulated, classical, and distribution flat-band voltage for 𝑡_f = 50 nm, 10 nm, and 2 nm is available in Figure 9, besides to the error versus the 𝑉_FBS. This analysis proofs that the model (8) with distributions is closer to the simulations than the classical model (1), which provides higher errors at lower thicknesses.

Figure 9 

The flat-band voltages: 𝑉FBS, 𝑉FBC, and 𝑉FBD, besides to the relative errors for 𝑉FBC, 𝑉FBD in respect to 𝑉FBS, for 𝑡f = 50, 10, and 2 nm.

Figure 10 comparatively presents the output characteristics when the drain-source voltage was increased from 0 V up to +5 V, at a constant 𝑉_GS, for two nanosizes of the SOI film.

Figure 10 

The ID-VDS characteristics at 𝑉GS = 3 V and rectangular shape of the SOI film with 10 nm and 2 nm thickness.

Besides to the model with distribution accuracy, the prior simulations of the statics characteristics highlights classical shape of characteristics for 𝑡_f > 10 nm and atypical shape for 𝑡_f < 10 nm.

Another direction of the SOI nanotransistors investigation is related to a special shape of the SOI film. Taking into account that the current occurs only at the Si-film bottom, results that the 90% from the upper Si-film region does not participate to conduction. Hence, this Si-film region was removed in next simulations, obtaining a SOI nanotransistor with a cavity or “U” shaped.

5. Simulation Results for Sub-10 nm Special Shaped SOI Nanotransistor without Interface Charges

In the simulations, the constructive data were those described in the paragraph 4. The aim of this paragraph is to highlight only the special shape effect of the semiconductor on the static characteristics.

The main physical effects included as “nanoeffects” were band to band tunnelling, Fowler-Nordheim tunnelling, Fermi distribution, including in the MODEL statement the following parameters: BBT, FNORD, and FERMI. Figure 11 presents the total current vectors in a structure with 𝑡_n+ = 7 nm, 𝑡_f = 1 nm, and 𝑡_BOX = 10 nm, at 𝑉_DS = 4 V, 𝑉_GS = 3 V, besides to the electrons concentration in the channel region. The vectors through the vacuum (emphasised by dotted line), proved the tunnel effect.

Figure 11 

Total current vectors in the 1 nm transistor.

In Figure 12 family of curves 𝐼_D-𝑉_GS for 𝑦_film = 200 nm, 10 nm, 1 nm, and 0.3 nm are presented. These curves have a maximum for 𝑦_film ≤ 1 nm, like SET transistor [19] or atypical nanodevices [20].

Figure 12 

The 𝐼D-𝑉GS transfer characteristics.

Figure 13 shows the curves 𝐼_D-𝑉_DS at 𝑉_GS = 3 V. The shape of the 𝐼_D-𝑉_DS curves with a minimum proves the tunnel effect, [21].

Figure 13 

The 𝐼D-𝑉DS output characteristics.

Figure 14 presents the global potential distribution (left) and a detail of the electron concentration (right) for the 0.3 nm structure with cavity, biased at a high drain voltage in this last case: 𝑉_S = 0 V, 𝑉_G = 3 V, and 𝑉_D = 4 V.

(a)

(b)

Figure 14 

The potential and the electron concentration in the 0.3 nm structure.

In this case, the saturation occurred, and an unbalanced electron distribution can be seen in the film 1.1·10¹⁶ cm⁻³ in the source region, 7·10¹⁵ cm⁻³ in the channel near the source, 2·10¹⁵ cm⁻³ in the channel near the drain, and decrease up to 1.4·10¹⁵ cm⁻³ in the drain, region at the film bottom; see Figure 14.

6. Possible Set Implementation

The single electron devices (SEDs) tend to become the main rivals for the sub-50 nm classical CMOS devices [22]. Advantages of SED’s are low-power dissipation, ultra-high-density of integration, a natural technology evolution inspired from miniaturized CMOS processes, and hence reasonable costs.

The simulations suggest the SET (single electron transistor) like behavior of the SOI nanotransistor with cavity for sub 1 nm film thickness. The electrons must be transferred from source to drain one by one [23].

As in the case of SOI-MOSFETs, a positive gate bias induces an electron inversion channel in the p-type film. The DC analysis used the following voltages: 𝑉_G = 3 V, 𝑉_D = 0.1 V, 𝑉_S = 0 V. The nanoeffects were simulated taking into account the Fowler-Nordheim tunneling and the Fermi distribution, using in the MODEL statement the following parameters: FNORD, FERMI: models conmob srh auger fermi fldmob fnord print, meaning: constant mobility, Shockley-Read-Hall and Auger recombination model and mobility attenuation with lateral field. For electron concentration study in the inversion channel, the drain voltage was maintained at 0.1V and the gate voltage was increased from 0 V to +3 V with a 0.05 V step. Despite of the very thin p film, a high electron concentration occurs in the channel at 𝑉_GS = +3 V, as is shown in Figure 15. With 𝑉_DS increasing, the current arise as a superposition, when the source-drain vacuum is tunneled.

Figure 15 

The electron concentrations in 0.3 nm SET: global.

However, the device is in strong inversion at this gate voltage, because 𝑛_channel=2 × 10²⁰ cm⁻³ > 5 × 10¹⁵ cm⁻³ = 𝑁_𝐴−film. The electron concentration in the 0.3 nm p-type SOI film is: 𝑛_channel= 2 × 10²⁰ cm⁻³ = 0.2 nm⁻³≈ 1 electron per channel volume, V, Figure 16. The channel volume is V = 0.3 nm × 3 nm × 6 nm = 5.4 nm³. Then, the electrons transport, from source to drain, is one by one. Therefore, the SET principle is satisfied.

Figure 16 

The electron concentrations in the 1 nm transistor-a detail in a cross-section.

7. Conclusions

This paper presented a nanotransistor with silicon on insulator structure in different situations. When the film thickness varied between 200 nm to 10 nm the electrical characteristics preserve the classical shape. When the film thickness varied from 1 nm to 0.3 nm and a cavity occurs above the film, the device presents atypical electrical characteristics 𝐼_D-𝑉_GS, having a maximum like the SET transistor. The shape of the 𝐼_D-𝑉_DS curves with a minimum proves the presence of the tunnel effect. The electron transport in the p-film is one by one, proving the Single Electron Technology for our proposed SOI nanotransistor.

Also, the new model with distribution presented in this paper, improves the flat-band voltage modeling of the SOI nanostructures, introducing new fitting parameters: Δ𝑡_1,2—the spreading coefficients. However, neither the presence or absence of the interface charge 𝑄_𝐼1,2 is defining for the atypical shape of the transfer characteristics, because the curves with maximum arose both in rectangular SOI film with 𝑄_𝐼2 both in “U” shape SOI film without 𝑄_𝐼2; the only conditions was to exist a ultra-thin SOI film under 2 nm.

The simulations revealed that the SOI nanotransistor with a thinner film in the channel body represents a solution for the SET’s implementation, with possible applications in industry like digital ULSI, invertors with SET, memories with SEM-single electron memory, and communications cells [24].

These simulations and the model with the distribution represent an important chapter in the devices design—a key stage during the industrial manufacturing.

Acknowledgment

The work has been cofunded by the Sectorial Operational Program Human Resources Development of the Romanian Ministry of Labor, Family, and Social Protection through the Financial Agreement nos. POSDRU/89/1.5/S/62557 and PNII-62063-12095.