Table of Contents Author Guidelines Submit a Manuscript
Journal of Nanomaterials
Volume 2011, Article ID 906237, 6 pages
http://dx.doi.org/10.1155/2011/906237
Research Article

Design and Analysis of a New Carbon Nanotube Full Adder Cell

1School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Engineering Campus, 11800 Penang, Malaysia
2Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Malaysia
3Department of Computer Engineering, Islamic Azad University, Ashtian Branch, 39618-13347 Ashtian, Iran

Received 10 January 2011; Accepted 27 February 2011

Academic Editor: Theodorian Borca-Tasciuc

Copyright © 2011 M. H. Ghadiry et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. Y. M. Lin, J. Appenzeller, J. Knoch, and P. Avouris, “High-performance carbon nanotube field-effect transistor with tunable polarities,” IEEE Transactions on Nanotechnology, vol. 4, no. 5, pp. 481–489, 2005. View at Publisher · View at Google Scholar · View at Scopus
  2. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, “Carbon nanotube field-effect transistors for high-performance digital circuits—DC analysis and modeling toward optimum transistor structure,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2711–2717, 2006. View at Publisher · View at Google Scholar
  3. A. M. Ionescu, “Electronic devices: nanowire transistors made easy,” Nature Nanotechnology, vol. 5, no. 3, pp. 178–179, 2010. View at Publisher · View at Google Scholar · View at Scopus
  4. J. P. Colinge, C. W. Lee, A. Afzalian et al., “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, no. 3, pp. 225–229, 2010. View at Publisher · View at Google Scholar · View at Scopus
  5. M. Taghi Ahmadi, H. Houg Lau, R. Ismail, and V. K. Arora, “Current-voltage characteristics of a silicon nanowire transistor,” Microelectronics Journal, vol. 40, no. 3, pp. 547–549, 2009. View at Publisher · View at Google Scholar · View at Scopus
  6. J. Deng and H.-S. P. Wong, “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part II: full device model and circuit performance benchmarking,” IEEE Transactions on Electron Devices, vol. 54, no. 12, pp. 3195–3205, 2007. View at Publisher · View at Google Scholar
  7. M. T. Ahmadi, R. Ismail, M. L. P. Tan, and V. K. Arora, “The ultimate ballistic drift velocity in carbon nanotubes,” Journal of Nanomaterials, vol. 2008, no. 1, Article ID 769250, 2008. View at Publisher · View at Google Scholar · View at Scopus
  8. C. Dwyer, M. Cheung, and D. J. Sorin, “Semi-empirical SPICE models for carbon nanotube FET logic,” in Proceedings of the 4th IEEE Conference on Nanotechnology, pp. 386–388, August 2004. View at Scopus
  9. M. Hayatia, A. Rezaeia, and M. Seifia, “CNT-MOSFET modeling based on artificial neural network: application to simulation of nanoscale circuits,” Solid-State Electronics, vol. 54, pp. 52–57, 2010. View at Google Scholar
  10. M. Ahmadi, J. F. Webb, Z. Johari, and R. Ismail, “Single wall carbon nanotube field effect transistor model,” Journal of Computational and Theoretical Nanoscience, vol. 8, no. 2, pp. 261–267, 2011. View at Google Scholar
  11. M. T. Ahmadi, Z. Johari, N. A. Amin, A. H. Fallahpour, and R. Ismail, “Graphene nanoribbon conductance model in parabolic band structure,” Journal of Nanomaterials, vol. 2010, Article ID 753738, 4 pages, 2010. View at Publisher · View at Google Scholar
  12. M. T. Ahmadi, M. L. P. Tan, R. Ismail, and V. K. Arora, “The high-field drift velocity in degenerately-doped silicon nanowires,” International Journal of Nanotechnology, vol. 6, no. 7-8, pp. 601–617, 2009. View at Publisher · View at Google Scholar · View at Scopus
  13. M. H. Ghadiry, H. Mohammadi, and M. N. Senejani, “Two new low power high performance full adder with minimum gates,” International Journal of Electrical and Information Engineering, vol. 3, pp. 124–131, 2009. View at Google Scholar
  14. K. Navi, M. Maeen, V. Foroutan, S. Timarchi, and O. Kavehei, “A novel low-power full-adder cell for low voltage,” Integration, the VLSI Journal, vol. 42, no. 4, pp. 457–467, 2009. View at Publisher · View at Google Scholar · View at Scopus
  15. V. Foroutan, K. Navi, and M. Haghparast, “A new low power dynamic full adder cell based on majority function,” World Applied Sciences Journal, vol. 4, pp. 133–141, 2008. View at Google Scholar
  16. M. Nadi, M. H. Ghadiry, and M. K. Dermany, “The effect of number of virtual channel on NOC EDP,” Journal of Applied Mathematics & Informatics, vol. 2010, pp. 539–551, 2010. View at Google Scholar
  17. M. H. Ghadiry, A. Khari, and M. N. Senejani, “A new full-swing full adder based on new logic approach,” World Applied Sciences Journal, vol. 1, 2011. View at Google Scholar
  18. M. H. Ghadiry, A. K. A'Ain, and M. N. Senejani, “Design and analysis of a novel low PDP full adder cell,” Journal of Circuits, Systems, and Computers, vol. 20, 2011. View at Google Scholar
  19. K. Navi, M. Rashtian, A. Khatir, P. Keshavarzian, and O. Hashemipour, “High speed capacitor-inverter based carbon nanotube full adder,” Nanoscale Research Letters, vol. 5, no. 5, pp. 859–862, 2010. View at Publisher · View at Google Scholar · View at Scopus
  20. M. N. Senejani, M. Hosseinghadiry, and M. Miryahyaei, “Low dynamic power high performance adder,” in Proceedings of International Conference on Future Computer and Communication (ICFCC '09), pp. 482–486, April 2009. View at Publisher · View at Google Scholar · View at Scopus
  21. K. Navi, A. Momeni, F. Sharifi, and P. Keshavarzian, “Two novel ultra high speed carbon nanotube Full-Adder cells,” IEICE Electronics Express, vol. 6, no. 19, pp. 1395–1401, 2009. View at Publisher · View at Google Scholar · View at Scopus
  22. K. Navi, R. S. Rad, M. H. Moaiyeri, and A. Momeni, “A low-loltage and energy-efficient full adder cell based on carbon nanotube technology,” Nano-Micro Letters, vol. 2, pp. 114–120, 2010. View at Google Scholar
  23. K. Navi, M. Maeen, V. Foroutan, S. Timarchi, and O. Kavehei, “A novel low-power full-adder cell for low voltage,” Integration, the VLSI Journal, vol. 42, no. 4, pp. 457–467, 2009. View at Publisher · View at Google Scholar · View at Scopus
  24. C. V. Nguyen, Q. Ye, and M. Meyyappan, “Carbon nanotube tips for scanning probe microscopy: fabrication and high aspect ratio nanometrology,” Measurement Science and Technology, vol. 16, no. 11, pp. 2138–2146, 2005. View at Publisher · View at Google Scholar · View at Scopus
  25. C. Wang, J. Zhang, K. Ryu, A. Badmaev, L. G. de Arco, and C. Zhou, “Wafer-scale fabrication of separated carbon nanotube thin-film transistors for display applications,” Nano Letters, vol. 9, no. 12, pp. 4285–4291, 2009. View at Publisher · View at Google Scholar · View at Scopus
  26. 2011, http://www.mosis.com/ibm/ibm_processes.html.
  27. S. Bobba, J. Zhang, A. Pullini, D. Atienza, and G. De Micheli, “Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '09), pp. 616–621, April 2009. View at Scopus
  28. S. Goel, A. Kumar, and M. A. Bayoumi, “Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1309–1321, 2006. View at Publisher · View at Google Scholar · View at Scopus
  29. J. F. Lin, Y. T. Hwang, M. H. Sheu, and C. C. Ho, “A novel high-speed and energy efficient 10-transistor full adder design,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, no. 5, pp. 1050–1059, 2007. View at Publisher · View at Google Scholar · View at Scopus