Journal of Nanomaterials

Volume 2012 (2012), Article ID 242459, 8 pages

http://dx.doi.org/10.1155/2012/242459

## Robustness Comparison of Emerging Devices for Portable Applications

^{1}Department of Electronics and Telecommunication Engineering, P.D.V.V.P College of Engineering, Ahmednagar 414 111, India^{2}Department of Electronics Engineering, AMU, Aligarh, India^{3}Vishwabharati Acadmey's COE, Sarola Baddi, Ahmednagar, India

Received 4 October 2011; Accepted 15 November 2011

Academic Editor: Christian Brosseau

Copyright © 2012 S. D. Pable et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

Extensive development in portable devices imposes pressing need for designing VLSI circuits with ultralow power (ULP) consumption. Subthreshold operating region is found to be an attractive solution for achieving ultralow power. However, it limits the circuit speed due to use of parasitic leakage current as drive current. Maintaining power dissipation at ultralow level with enhanced speed will further broaden the application area of subthreshold circuits even towards the field programmable gate arrays and real-time portable domain. Operating the Si-MOSFET in subthreshold regions degrades the circuit performance in terms of speed and also increases the well-designed circuit parameter spreading due to process, voltage, and temperature variations. This may cause the subthreshold circuit failure at very low supply voltage. It is essential to examine the robustness of most emerging devices against PVT variations. Therefore, this paper investigates and compares the performance of most promising upcoming devices like CNFET and DG FinFET in subthreshold regions. Effect of PVT variation on performance of CNFET and DG FinFET has been explored and it is found that CNFET is more robust than DG-FinFET under subthreshold conditions against PVT variations.

#### 1. Introduction

ULP applications like pacemakers, hearing aids, body-based sensor networks, wireless sensor networks, and many other biomedical systems are bounded by ULP budget rather than the higher performance. Supply voltage scaling is a well-established technique for reducing the power consumption significantly since energy has squared dependency on . Under extreme voltage scaling, the is reduced to the threshold voltage of the MOSFET. Under this condition, the power consumption is significantly reduced up to milli Watt range but the speed of such circuits degrades substantially. This region of operation of a Si-MOSFET is popularly known as a subthreshold region. Under subthreshold conditions, the parasitic off-state leakage current of a MOSFET is utilized as the switching current for designing ULP circuits. It is possible to reduce the power consumption further under deep subthreshold but the delay penalty rises exponentially.

Subthreshold circuits also exhibit improvement in transconductance due to exponential characteristics, smaller gate capacitance, and near-ideal voltage transfer characteristics (VTC). Previous research on subthreshold operation of Si-MOSFET shows that subthreshold circuits are more appropriate for ULP and moderate throughput applications [1–4]. Recently, while designing low-power circuits, importance is given to operate the device at minimum energy delay point (EDP) instead of minimum energy point (MEP). It is observed from Figure 1 that minimum EDP of an inverter with a fan out of four loading occurs in the subthreshold region with 32 nm Si-MOSFET [5]. For combinational circuits penalty in delay is significant. Therefore, the key challenges for the subthreshold circuit designer are (a) to improve the speed and (b) to reduce device variability.

Due to reduced speed and variability issues in Si-MOSFET, it is important to investigate the potential of upcoming devices for enhancing the performance of subthreshold circuits for real-time applications where performance cannot be ignored. Device parameter variations under subthreshold conditions are significant and may cause the circuit failure. FinFET and CNFET transistors are evolving rapidly, and it is expected that these devices will replace the existing bulk CMOS technology in the future [6]. To the best of our knowledge, no prior publication has modeled the delay, switching energy, and variability of FinFET and CNFET devices under subthreshold conditions at ULP levels on the same platform.

The organization of this paper is as follows. Section 2 introduces the device design metric parameters considered for comparison purpose. Section 3 explores the DG FinFET structure. Section 4 explores the optimisation of number of tubes per device and inter-CNT pitch for optimum value of delay and energy. Section 5 extensively compares the subthreshold performance and the effect of PVT variation on CNFET- and FinFET-based inverter. Section 6 concludes this paper.

#### 2. Device Design Metric under Subthreshold Conditions

CNFET and DG-FinFET are the most promising emerging nanodevices. However, for extending their application area even for ULP, there is a need to explore the reliability of these devices in the presence of PVT variations for future ULP circuits.

The subthreshold operating region uses small parasitic off-state leakage current as a switching current to realize ULP circuits. For Si-MOSFET device, this small leakage current can be expressed as follows [1]: where “” is the transistor threshold voltage, “” is the subthreshold slope factor , “” is the thermal voltage, and “” is the DIBL coefficient.

The ON-OFF current ratio is an important device performance metric that mainly decides the power dissipation of the device. is the subthreshold leakage current at , and is the leakage current at V and . For better performance, higher subthreshold ON-OFF current ratio is preferred. The subthreshold slope is another important device design metric that determines the relationship between subthreshold leakage current and gate voltage. From the definition of inverse subthreshold slope, it can be expressed as follows [7]: The gate delay and switching energy in terms of “” and load capacitance is given by [8]

It is clear from (3) and (4) that the time delay and switching energy are proportional to “” and the load capacitance. It is essential to optimize device parameters for better value of “” for lower delay and switching energy. Due to the performance challenges inherently present in Si-MOSFET under subthreshold conditions it is necessary either to optimize the Si-MOSFET device parameters or to explore FinFET or CNFET for ULP applications. Our previous work on subthreshold FPGA has successfully optimized the Si-MOSFET for better performance under subthreshold conditions [9]. Device and circuit performance parameters to be considered for designing better subthreshold circuits are subthreshold leakage current, , “”, , gate delay, total power consumption, dynamic energy, and static noise margin. The next sections describe the FinFET device structure followed by optimization of CNFET device parameters for fair performance comparison (equal and width) with that of FinFET.

#### 3. Structure of DG FinFET Device

A FinFET transistor is a vertical double-gate emerging device with a potential to replace bulk devices at nanometer technology node [10–12]. The structure of the subcircuit model of a FinFET device used for simulation is as illustrated in Figure 2. A FinFET is modeled as a pair of FD SOI device with source and drain connected together as shown in Figure 2(c). The DG FinFET can either have a three-terminal (3T) configuration, where both the gates are shorted, or a four-terminal (4T) configuration, having fixed back-gate bias and the front gate acting as the control electrode. In this work, three-terminal symmetric FinFET is considered because it has better drive current as compared to other configurations [10]. Device parameters used for FinFET simulation are as listed in Table 1.

#### 4. Optimisation of CNFET under Subthreshold Conditions

CNFET provides many potential advantages like improved channel transport and high carrier velocity of CNT, which results in significant improvement in speed over Si-MOSFET [13–15]. Single wall carbon nanotube can be visualized as a sheet of graphite that is rolled up and joined together as shown in Figure 3(a). A typical layout of a MOSFET-like CNFET device is illustrated in Figure 3(b). As shown in Figure 3, the CNTs are placed on the bulk substrate () and a high () dielectric separates the CNTs from metal gate electrode by an insulator thickness “,” with dielectric constant of 16. “” is the width of metal gate, channel length nm, and source drain under-lapped nm. The power dissipation and speed of CNFET devices are mainly governed by the number of tubes in the channel , tube diameter, and inter-CNT pitch. Hence, there is a need to explore the best possible values of “” and “pitch” for better device and circuit performance in ULP regions for a given tube diameter. Various CNFET models have been developed for future deep nanometer technology [13, 14]. The impact of scattering on BTBT is not taken into account in CNFET compact model developed in [14], and this effect can be of importance. Therefore, the experimentally validated Stanford University CNFET model is used for simulating the CNFET device [13]. The chirality vector (19, 0) is chosen for the CNT, which corresponds to 1.5 nm tube diameter and of 0.29 V for CNFET.

To design better reconfigurable ULP circuits, it is necessary to explore the performance and impact of CNFET technology parameter variations on circuit characteristics. The drive current, and hence the speed of CNFET, is a function of number of tubes per device , device transconductance, , , and voltage drop across the doped source region . The is determined by the CNT diameter and is constant for a given diameter.

The CNFET delay and switching energy are given by [16] is the gate capacitance of CNFET. The total gate capacitance of CNFET with the number of tubes “” is given by [16] where “” is the width of CNFET, “” is the gate length, and “” includes fringing capacitance.

It is important to optimize the number of tubes and inter-CNT pitch (“”) for optimum performance of a CNFET device. To achieve optimum values of “” and “,” “” and the gate capacitance (“”) are plotted for different values of “” and “” ratio as shown in Figure 4. The CNFET pitch “” and the number of tubes “” are varied by keeping 32 nm device width constant. It is evident from Figure 4 that by using nm and , minimum values of “” and “” with moderate drive current are obtained. The impact of “” and “” on delay and dynamic energy of a five-stage inverter chain is also investigated. The delay, dynamic energy, and power dissipation are measured for the third inverter in a chain for more realistic comparison [16] and are shown in Figures 5 and 6, respectively. It is evident from (4), (5) and Figures 5 and 6 that the device having minimum “” and “” shows minimum delay, power dissipation, and dynamic energy. Therefore, for further performance analysis of the CNFET device and circuits, nm and are considered.

#### 5. Performance Comparison of Emerging Devices under Subthreshold Conditions

It is well established that subthreshold circuits are more prone to PVT variations [1–4]. To better understand the effect of PVT variations, the analysis of FinFET and CNFET begins with a focus on device level characteristics first and then the circuit level performance characteristics are explored. Switching threshold and signal to noise margin (SNM) are obtained from the VTC curves. VTC comparison of CNFET- and FinFET-based inverter is shown in Figure 7 for the same width and with input voltage being scaled down. It is observed that CNFET-based circuits have steeper VTC with switching threshold voltage of 0.1 V and that of FinFET is 0.093 V. This is due to ballistic transport of carriers in CNFET.

From (3) and (4), “” and “” play an important role in determining the speed and switching energy. Hence, it is important to investigate the impact of width and scaling on “” and “.” Figure 8 shows the comparison of “” and “” for CNFET and FinFET for different widths at 0.2 . The width of CNFET device is varied by changing the value of “” [16] and keeping inter-CNT pitch constant. The parasitic capacitance is proportional to device width in FinFET [17]. Hence, the parasitic capacitance starts dominating the intrinsic gate capacitance with increasing width, thereby increasing “” significantly. In case of CNFET, the “” increases due to the increase in both “” and width of CNFET as from (7). It is clear from Figure 8 that the minimum size of FinFET has almost 3.25X higher “” than CNFET, which is a major cause of higher power and dynamic energy consumption in case of FinFET as compared to CNFET. It is also observed from Figure 8 that by increasing the device width, “” of both devices increases slightly. It is evident from Figure 8 that FinFET shows better “” than CNFET due to its dual gate geometry structure. Though gate leakage power (GPL) is small in subthreshold regions as compared to superthreshold regions, it is also essential to estimate the same for energy constrained applications. Figure 9 shows “GLP” and “” as a function of . It has been observed that “GLP” of CNFET is almost 5.85X lower than that of FinFET at V. This is due to the absence of dangling bonds and hence suppressed carrier scattering in case of CNFET.

To compare robustness, it is necessary to study the impact of , , , and temperature variation on CNFET and FinFET. Table 2 compares the effect of ±10% PVT variation [17] on different device parameters. It is evident from Table 2 that the drive current in CNFET is a weak function of “” and “” variations due to ballistic transport of carriers [18].

The effective drive capacitance in CNFET is mainly dominated by fringing capacitance, and, therefore, it is less sensitive to geometry parameters such as “” and “” [18] compared with FinFET. However, it is a strong function of compared with case of FinFET due to ballistic transport of carriers. Figures 10 and 11 show the impact of ±15% “” and “” variations on “” and gate capacitance, respectively. It is evident from Figure 10 that as “” scales down, “” of CNFET and FinFET improves. This is because when “” reduces, the gate obtains better control over the channel. It is clear from Figure 11 that the “” of FinFET is almost independent of “” variation. This is due to the fact that the dominating gate overlap and fringing capacitances, which are major contributors to “,” are “” independent. Hence, the delay dependency on “” is mainly due to the ON current. However, from (7) and Figure 11, it is observed that the “” of CNFET increases with the increase in “”.

It is also important to explore the effect of PVT variations on circuit performance parameters such as delay and switching energy. The FO4 inverter chain is used as a test bench. Delay and switching energy is measured across the third inverter [16]. Appropriate device size is chosen for equal rise and fall time. CNFET and FinFET show 11.9% and 28% variation in delay and 8.5% and 19.1% variation in switching energy, respectively, for ±10% variation in “” as depicted in Figures 12 and 13, respectively. Reducing “” in CNFET decreases the “” by 2.57% and increases the ON current by 10%. However, the “” also increases by 5%. Hence, “” variation has little impact on delay and switching energy of CNFET. In case of FinFET, “” of both front gate and back gate is varied. As the is reduced, the parasitic capacitances start dominating the intrinsic gate capacitance and hence increase the overall “.” The current increases by 16.91% for 20% reduction in , which results in increase in circuit delay in case of subthreshold circuits [17].

Subthreshold leakage current is also sensitive to “” of the device. Assuming proportional lithographic scaling, the length of the source and drain region is considered to be equal to the “” [16]. The drive current of CNFET decreases by 12% as gate length reduces by 20%. It is also observed that in CNFET, there is negligible change in as compared to FinFET for “” variation. Total “” is proportional to gate length and increases by 13% by increasing the “” by ±10% as shown in Figure 11. Hence, “” variation in CNFET has little impact on delay as shown in Figure 14. “” almost remains constant by varying the “,” and from Figure 15 it is also observed that switching energy is less affected by “” variation.

In DG FinFET, the reduction in “” increases the subthreshold current by 40.56% for ±10% “” variation. This is due to pronounced short channel effect [18], which improves the circuit performance in terms of delay as depicted in Figure 14. For FinFET, as “” decreases, the “” increases by 2.33% as shown in Figure 13, and ratio decreases significantly due to increase in current (47.87% for ±10%). This results in the consumption of more switching energy as shown in Figure 15. From the above analysis, it is observed that CNFET-based circuit performance metrics experience less variation due to “” because of ballistic transport of carriers. CNFET is also found to be more robust against variation. This is due to the fact that the effective drive capacitance in CNFET device is mainly dominated by the fringing capacitance. Hence, the CNFET device is found to be more robust against geometry-based parameter variations over FinFET device.

To evaluate the robustness of subthreshold circuits, SNM is important. SNM is defined as the point where [17]. To explore the impact of PVT parameter variation, we have assumed ±10% variation in “,” , , and temperature [17]. Table 3 shows the detailed SNM comparison of CNFET and FinFET inverter. It is evident from Table 3 that CNFET shows less impact against “,” , and variations on SNM than DG FinFET. This is due to device geometry, ballistic transport of carriers, and independency on temperature, respectively. For DG FinFET, as temperature increases, “” increases and reduces significantly. Hence, upon increasing temperature, SNM and switching threshold voltage are significantly affected. However, in CNFET, SNM variation is less due to temperature variation because of high thermal stability property of CNFET. Due to the above-mentioned properties of CNFET, “” of CNFET is not affected significantly unlike FinFET due to PVT variation. However, SNM of both devices are greatly affected by variations. It can be observed from Table 3 that CNFET shows better SNM and, hence, switching threshold voltage over DG FinFET. Hence, CNFET is more robust than DG FinFET in terms of noise margin and gain.

#### 6. Conclusions

Performance challenges inherently associated with Si-MOSFET under subthreshold conditions led to the need of investigating alternative devices for better system performance. This paper successfully explored the performance and robustness against PVT variations of CNFET and DG FinFET devices. Analysis of subthreshold slope and gate capacitance of CNFET device shows that performance of CNFET circuits can be greatly improved by number of tubes and pitch for minimum subthreshold slope and gate capacitance. PVT variability analysis of CNFET and DG FinFET devices is carried out successfully. CNFET drive current and performance parameters are less sensitive to channel length, oxide thickness, and temperature variation over FinFET. Sensitivity of CNFET devices is slightly higher than that of FinFET for variation.

#### Acknowledgment

This work is funded by grants received from Department of Science and Technology (DST), Government of India under their FIST programme.

#### References

- H. Soeleman, K. Roy, and B. C. Paul, “Robust subthreshold logic for ultra-low power operation,”
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, vol. 9, no. 1, pp. 90–98, 2001. View at Google Scholar - S. K. Gupta, A. Raychowdhury, and K. Roy, “Digital computation in subthreshold region for ultralow-power operation: a device-circuit-architecture codesign perspective,”
*Proceedings of the IEEE*, vol. 98, no. 2, pp. 160–190, 2010. View at Publisher · View at Google Scholar · View at Scopus - A. Wang, B. H. Calhoun, and A. P. Chandrakasan,
*Sub-Threshold Design for Ultra Low-Power Systems*, Springer, New York, NY, USA, 1st edition, 2006. - B. H. Calhoun, J. F. Ryan, S. Khanna, M. Putic, and J. Lach, “Flexible circuits and architectures for ultralow power,”
*Proceedings of the IEEE*, vol. 98, no. 2, pp. 167–282, 2010. View at Publisher · View at Google Scholar · View at Scopus - http://www.eas.asu.edu/ptm/.
- M. Dragoman and D. Dragoman,
*Nano Electronics-Principles and Devices*, Artech House, Boston, London, 2nd edition, 2010. - J. J. Kim and K. Roy, “Double gate-MOSFET subthreshold circuit for ultralow power applications,”
*IEEE Transactions on Electron Devices*, vol. 51, no. 9, pp. 1468–1473, 2004. View at Publisher · View at Google Scholar · View at Scopus - H. Soeleman, M. Seok, D. Sylvester, and D. Blaauw, “Nanometer device scaling in subthreshold logic and SRAM,”
*IEEE Transactions on Electron Devices*, vol. 55, no. 1, pp. 175–185, 2008. View at Publisher · View at Google Scholar - S. D. Pable and M. Hasan, “High speed interconnect through device optimization for subthreshold FPGA,”
*Microelectronics Journal*, vol. 42, no. 3, pp. 545–552, 2011. View at Publisher · View at Google Scholar - W. Zhao and Y. Cao, “Predictive technology model for nano-CMOS design exploration,”
*ACM Journal on Emerging Technologies in Computing Systems*, vol. 3, no. 1, pp. 1–17, 2007. View at Google Scholar - H. T. Stephen, P. Xuan, J. Bokor, and H. Chenming, “Comparison of short-channel effect and offstate leakage in symmetric vs. asymmetric double gate MOSFET,” in
*Proceedings of the IEEE International SOI Conference Proceedings*, pp. 30–31. - R. Vaddi, S. Dasgupta, and R. P. Agarwal, “Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic,”
*Microelectronics Journal*, vol. 41, no. 4, pp. 195–211, 2010. View at Publisher · View at Google Scholar · View at Scopus - J. Deng and A. Wang, “A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—part I: model of the intrinsic channel region,”
*IEEE Transactions on Electron Devices*, vol. 54, no. 12, pp. 3186–3194, 2007. View at Publisher · View at Google Scholar · View at Scopus - S. Frégonèse, C. Maneux, and T. Zimmer, “Implementation of tunneling phenomena in a CNTFET compact model,”
*IEEE Transactions on Electron Devices*, vol. 56, no. 10, pp. 2224–2231, 2009. View at Publisher · View at Google Scholar · View at Scopus - H. S. P. Wong, J. Deng, A. Hazeghi, T. Krishnamohan, and G. C. Wan, “Carbon nanotube transistor circuits-models and tools for design and performance optimization,” in
*Proceedings of the International Conference on Computer-Aided Design (ICCAD '06)*, pp. 651–654, November 2006. View at Publisher · View at Google Scholar · View at Scopus - N. Patil, J. Deng, S. Mitra, and P. H. S. Wong, “Circuit-level performance benchmarking and scalability analysis of carbon nanotube transistor circuits,”
*IEEE Transactions on Nanotechnology*, vol. 8, no. 1, pp. 37–45, 2009. View at Publisher · View at Google Scholar · View at Scopus - R. Vaddi, S. Dasgupta, and R. P. Agarwal, “Device and circuit co-design robustness studies in the subthreshold logic for ultralow-power applications for 32 nm CMOS,”
*IEEE Transactions on Electron Devices*, vol. 7, no. 3, pp. 654–664, 2010. View at Google Scholar - B. C. Paul, S. Fujita, M. Okajima, and T. Lee, “Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits,”
*IEEE Electron Device Letters*, vol. 27, no. 5, pp. 380–382, 2006. View at Publisher · View at Google Scholar · View at Scopus