Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs

Abstract

Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in silicon MOSFET while sustaining the same unit area at higher current density.

1. Introduction

Carbon nanotubes (CNTs) are gaining momentum in the current silicon technology as a complementary nanostructure that could reform the device architecture. CNT modeling has been rigorously studied and examined [1–5] to assess the performance of the device at the circuit level. Advancement of the nanotechnology devices modeling is vital for the foreseeable future of carbon nanotube as switching device, interconnect and memory in integrated circuits (ICs). An in situ growth single-walled carbon nanotube (SWCNT), which integrates long channel 600 nm CNT channel, thin Al₂O₃ top gate contact, and Palladium (Pd) metal source/drain contacts, has been demonstrated [6].

In addition, we report the potential of long channel 65 nm CNT as substitute to 45 nm silicon metal-oxide semiconductor field-effect transistor (Si MOSFET) from the perspective of modeling for future CNT-logic applications. We observe good agreement between CNTFET and Si MOSFET, respectively, when simulating two-terminal drain current–voltage (𝐼_𝑑-𝑉_𝑑) characteristic. The projection has shed light on the reduction of DIBL and high field effects [7] as well as reduction in long channel CNT which is a widespread phenomenon in nanoscale Si MOSFET [8, 9]. We also demonstrate the effects of the channel area restructuring on the maximum electric field as well as density of states (DOS) in the conductance of CNT. Unlike MOSFET, it is revealed that the performance of CNT is enhanced when the source and drain width is minimized rather than the length, primarily due to the gate-to-source-drain parasitic fringe capacitances [10]. MOSFET scaling in accordance with Moore’s Law will reach its fundamental limitation as a result of process controllability in the next 10 years. Consequently, it is necessary to ensure that novel material is studied to provide alternatives to the current technologies and challenges in the new era of nanotechnology.

2. Carbon Nanotube and MOSFET Modeling

The layout of a CNTFET device is depicted in Figure 1. The area of the channel is given by the multiplication of the width, 𝑊, of the source and drain contact and the length, 𝐿, of the nanotube [6]. Details of the quasiballistic MOSFET device modeling can be found in previous work in [11, 12].

Figure 1 

The unit area size of CNT channel with source and drain.

The carbon nanotube model [13] is a unified nanostructure model based on quantum transport theory established by Datta [14]. This work extended the universal DOS spectral function [15] into the numerical calculation for CNT conduction subbands. We have included multiband density of states to account for multimode transport [16]. For an accurate simulation, the input parameters shown in Table 1 for MOSFET and CNTFET are extracted from TSMC [17] and Javey et al. [18], respectively. The 60 nm nanotube device model incorporate quasiballistic transport scattering as confirmed by [18]. At 60 nm length, the carriers travelling on the CNT surface have smaller mean free path than acoustic phonon which occurred at 300 nm.

Table 1 

Device model input and output parameter at 𝑉_𝐺=1 V.

The typical width of a high-tech CNTFET device is reported [10] to be 1 μm. The width of the CNT is calculated to be 𝑊_CNT=𝐴_MOS/𝐿_C, when both CNT and MOSFET devices are having identical channel area (𝐴_MOS=𝐴_CNT). In a case when both devices can provide same level of current, channel area becomes 𝐴=(𝑘𝐿)² when given the scaling factor; 𝑘 and both parameter 𝑊=𝐿. CNT channel with length, 2𝑘𝐿_CNT, can provide the same current with 𝑊_CNT=0.5𝐿_CNT. Even when the physical widths of the CNT channel, 𝑊≤0.5𝑘𝐿_CNT, there is no area drawback provided 𝐿≥2𝑘𝐿_CNT. As nanotube channel length increases, maximum electric field in CNT, 𝐸_𝑚CNT reduces tremendously [19, 20]. As for CNT with 𝐿=60 nm, the maximum electric field is found to be 𝐸_𝑚=(3/4)𝐸_𝑚Si.

In the 𝐼_𝑑-𝑉_𝑑 simulation of CNTFET, Landauer-Buttiker formalism is utilized [21]. The drain current, 𝐼_𝑑 is given as 𝐼_𝑑𝑉_𝐺,𝑉_𝑑,𝑉_𝑠=𝐺_ON𝑘_𝐵𝑇𝑞𝑞𝐸log1+exp^𝐹−𝑉_sc𝑉_𝐺,𝑉_𝑑,𝑉_𝑠𝑘_𝐵𝑇−𝐺_ON𝑘_𝐵𝑇𝑞×𝑞𝐸log1+exp^𝐹−𝑉_sc𝑉_𝐺,𝑉_𝑑,𝑉_𝑠−𝑉_𝑑−𝑉_𝑠𝑘_𝐵𝑇, (1) where 𝐺_ON is the ON-conductance, 𝑉_sc is the channel potential, 𝐸_𝐹 is the Fermi energy, 𝑘_𝐵 is the Boltzmann Constant, 𝑇 is the temperature, 𝑞 is the charge of an electron, 𝑉_𝐺 is the gate voltage, 𝑉_𝑑 is the drain voltage, and 𝑉_𝑠 is the source voltage.

The quantum conductance limit of a ballistic SWCNT is 𝐺_ON=4𝑞²/ℎ. The theoretical framework of (1) derivation can be found in [19, 20]. The quasi-one-dimensional (Q1D) density of state function of CNT [22] is given by 𝐷(𝐸)=2𝑔_𝑣𝑔_𝑠3𝜋𝑎_cc𝑡_𝑖𝐸𝐸²−𝐸_𝐺/2², (2) where 𝑎_cc=1.42Å and 𝑡=3eV is the carbon-to-carbon (C–C) bonding energy, 𝐸_𝐺 is the bandgap energy, 𝑔_𝑠 is the spin degeneracy, and 𝑔_𝑣 is the valley degeneracy. On the other hand, the 𝐼_𝑑-𝑉_𝑑 characteristics for a short channel MOSFET can be expressed as 𝐼_𝑑=𝐶_𝐺𝜇_ℓ𝑓𝑊_MOS𝐿𝑉_𝐺−𝑉_𝑇−(1/2)𝑉_𝑑𝑉_𝑑1+𝑉_𝑑/𝑉_𝑐,0≤𝑉_𝑑≤𝑉_𝑑sat, (3) where 𝐶_𝐺 is the gate capacitance, 𝜇_ℓ𝑓 is the gate-field dependent mobility, 𝑉_𝑑sat is the saturation voltage at the point of current saturation, 𝑉_𝑐 is the critical voltage, and 𝑉_𝑇 is the threshold voltage. At current saturation, (3) becomes 𝐼_𝑑sat=𝛼𝐶_𝐺𝑉_𝐺−𝑉_𝑇−𝑉_𝑑sat𝑊𝑣_sat,𝑉_𝑑≥𝑉_𝑑sat, (4) where 𝛼=𝑣_𝐷/𝑣_sat is ratio of drift velocity, 𝑣_𝐷 with saturation velocity and 𝑣_sat at the drain [11, 23].

3. Results and Discussion

Figure 2 shows the density of states for Q1D of [20,0] zigzag CNT with three van Hove singularities. As the energy span widens, more electrons are capable of occupying the singularities pinned between source and drain Fermi levels.

Figure 2 

Electronic density of states calculated for [20,0] zigzag nanotubes.

In the 𝐼_𝑑-𝑉_𝑑 simulation, the source Fermi energy is set to be at 0.22 eV below the conduction band. Our simulation results in Figure 3 which comes from (1) indicate that the CNT is able to offer drain current performance comparable to a 45 nm Si MOSFET. Remarkably, the effective current per unit dimension yielded 53.5 times more of Si channel because of the small diameter tube.

Figure 3 

Drain characteristic of 60 nm single-walled carbon nanotube (colour solid lines) and 45 nm MOSFET (diamonds) with 0.1 V gate increment. Initial 𝑉𝐺 for MOSFET is 0.4 V (bottom).

The DIBL effects is suppressed fairly well for both devices with a slight advantage to CNT. Silicon demonstrated a superior subthreshold swing at 32.37 mV/dec, a value half of CNT. Although CNT has a lower on current, it sustains a high on-off ratio in 4 orders of magnitude. In addition to the device simulation, a SWCNT with a channel length of 600 nm is fabricated and shown in Figure 4. The Paladium contacts are made by electron beam lithography on SWCNT grown by thermal CVD from catalyst islands.

Figure 4 

Plan view of SWCNT formed between Palladium source and drain contact.

The 𝐼_𝑑-𝑉_𝐺 measurement was carried out on a back gate geometry ≈200 nm SiO₂ depicted in Figure 5. From Figure 3, the gate characteristic, 𝐼_𝑑-𝑉_𝐺, can be generated for the 60 nm CNT model and it is illustrated in Figure 6. The DIBL for the experimental data is at 1453 mV/V, while SS is estimated to be 664 mV/dec. Nevertheless, the 600 nm fabricated CNT is compensated by a high off-on ratio at 3.2×10⁴. It is found that DIBL can be lowered by at least one order of magnitude by doping the source end region of the channel [24] or the whole CNT [25, 26].

Figure 5 

Gate characteristics measurement of a 600 nm CNT from 𝑉𝑑=0.05 to 𝑉𝑑=1.0 V.

Figure 6 

Gate characteristics of a 60 nm CNT model from 𝑉𝑑=0.1 to 𝑉𝑑=1.0V in 0.1 V increment.

4. Conclusion

It is revealed that long channel CNT can deliver drain current comparable to a MOSFET. The carrier density along the CNTFET is at least 50 times that of the Si MOSFET. In the same channel area, CNT has better control of short channel effect (SCE) than Si as it has lower 𝐸_𝑚. This brings an enormous advantage since lower 𝐸_𝑚 has a smaller DIBL. A double gate or a cylindrical gate structure has the best control to suppress DIBL [27]. Based on this, we could have lower off-current in the transistor. As a result, a CNT uses less power consumption as a switching device when operating at the same frequency as a MOSFET.

Acknowledgments

MLPT thanks the Ministry of Higher Education Malaysia and the Universiti Teknologi Malaysia (UTM) for the award of advanced study fellowship leading to a Ph.D. degree at the University of Cambridge. This work is partially supported by UTM Research University Grant vot no. Q.J130000.2623.09J21 and Fundamental Research Grant Scheme (FRGS/2/2013/SG02/UTM/02/2). MLPT is also immensely grateful to Aun Shih Teh for providing the experimental data of SWCNT. The author also thanks the Research Management Centre (RMC) of UTM and Centre for Advanced Photonics and Electronics (CAPE), Cambridge, UK, for providing an excellent research environment to complete this work.