Research Article  Open Access
Enhanced Device and CircuitLevel Performance Benchmarking of Graphene Nanoribbon FieldEffect Transistor against a NanoMOSFET with Interconnects
Abstract
Comparative benchmarking of a graphene nanoribbon fieldeffect transistor (GNRFET) and a nanoscale metaloxidesemiconductor fieldeffect transistor (nanoMOSFET) for applications in ultralargescale integration (ULSI) is reported. GNRFET is found to be distinctly superior in the circuitlevel architecture. The remarkable transport properties of GNR propel it into an alternative technology to circumvent the limitations imposed by the siliconbased electronics. Budding GNRFET, using the circuitlevel modeling software SPICE, exhibits enriched performance for digital logic gates in 16 nm process technology. The assessment of these performance metrics includes energydelay product (EDP) and powerdelay product (PDP) of inverter and NOR and NAND gates, forming the building blocks for ULSI. The evaluation of EDP and PDP is carried out for an interconnect length that ranges up to 100 μm. An analysis, based on the drain and gate currentvoltage ( and ), for subthreshold swing (SS), draininduced barrier lowering (DIBL), and current on/off ratio for circuit implementation is given. GNRFET can overcome the shortchannel effects that are prevalent in sub100 nm Si MOSFET. GNRFET provides reduced EDP and PDP one order of magnitude that is lower than that of a MOSFET. Even though the GNRFET is energy efficient, the circuit performance of the device is limited by the interconnect capacitances.
1. Introduction
The number of transistors on a typical 1 × 1 cm chip has grown exponentially with twofold increase every 18 months keeping Moore’s Law [1] on track. Serious hindrances are in sight as transistor scaling enters the nanometer domain. Shortchannel effects are significant as devices are scaled below sub100 nm, providing challenges and opportunities for device and process engineers. Researchers across the globe are exploring new nanomaterials with transformed architecture to circumvent the roadblocks of siliconbased nanotechnology for enhanced circuit performance. Interconnects also play a key role as channels reach nanometer scale and resistance surge takes on an increasing importance [2]. Carbonbased allotropes offer a distinct advantage in a variety of applications [3–8]. Graphene nanoribbons (GNRs) are onedimensional (1D) nanostructures restricting carrier motion in only one direction, reducing scattering for enhanced mobility [6, 9]. The transistor current is quite high as electrons are injected from the source and transit to the drain terminal [6, 10–12]. A narrow width semiconducting GNR is utilized as a channel in a topgated transistor [13–15]. This pushes the limits of complementary metaloxidesemiconductor (CMOS) type of technology beyond its limits in a GNR. This paper focuses on modeling, simulation, and benchmarking of topgated graphene nanoribbon fieldeffect transistors (GNRFETs) against MOSFET. In addition, the evaluation of logic performance is carried out for both devices. It is observed that there is a good agreement between GNRFET and MOSFET based on the drain currentvoltage () characteristics. The energydelay product (EDP) and powerdelay product (PDP) are the performance metrics that represent the energy efficiencies of GNRFET and MOSFET logic gates. The simulations in this work are carried out for the 16 nm manufacturing processes. In the following, device model framework of our previous work [7, 16–19] is extended for the simulation and analysis of GNRFET and MOSFET at 16 nm node. Circuitlevel models of GNRFET are benchmarked against MOSFET. Logic performances of carbon and siliconbased inverter and NAND and NOR gates are assessed. For a fair assessment, the same channel length, nm, is adopted for GNRFET, PMOS, and NMOS. The device modeling is carried out in MATLAB and circuit development and simulation is performed using HSPICE and Cosmoscope.
2. Device Modeling
The simulated silicon MOSFET is based on Berkeley shortchannel IGFET model (BSIM) which was the standard model for deep submicron CMOS circuit design in the early 2000s [20]. IC companies including Intel, IBM, AMD, National Semiconductor, and Samsung widely use the chargebased model as an electronic computeraided design (ECAD) tool. BSIM4 version 4.7 MOSFET model is utilized in the simulation of NMOS and PMOS [21] in the present assessment. The top view of GNRFET with source and drain contacts is depicted in Figure 1. Various values of and (see Figure 2) are given in Table 1.

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3. Proposed Layout and Design
The interpolated contact size and spacer size of 16 nm node process technology are illustrated in Figures 2(a) and 2(b), respectively.
The channel width, , is a function of and S as given by
Table 1 gives design specifications for channel lengths from 16 to 180 nm range.
4. Analytical Modeling of GNRFET
In this section, the analytical model of GNRFET is derived. The channel surface potential , or selfconsistent voltage as is commonly known, is solved numerically in MATLAB using NewtonRaphson algorithm to obtain the voltage potential at the top barrier along the channel [23]. The is given by where is the total sum of capacitance at all the four terminals and is the total charge. is the additional charge due to the increase of . is the potential appearing across the channel region and is existing across the parasitic regions. The other symbols in (2) are given as follows where is the density of positive velocity states, is the density of negative velocity states and is the electron density at equilibrium: The carriers obey the FermiDirac probability distribution as follows: where and are defined as The onedimensional (1D) density of state (DOS) function in (4) is defined as where nm is the C–C bond length and eV is the C–C bonding energy. In (6), is the bandgap energy, is the spin degeneracy, and is the valley degeneracy. In an armchair GNR (aGNR), . A nonlinear regression model of is obtained through the use of the polynomial fit [24, 25]. The nonlinear approximation for dependence on and in the form of fifthorder polynomial is given to replace the NewtonRaphson algorithm in (2). The regression model is given as where , , , , , , and are the coefficients extracted from MATLAB curve fitting tool.
The coefficients to in Table 2 are empirical parameters used for curve fitting (2).

HSPICE utilizes (8) to simulate the drain and gate characteristic of GNRFET and MOSFET. The noniterative model allows crossplatform simulation, shorter execution time, and reduced computational cost [26]. In GNRFET, when gate and drain voltages are applied, is reduced by . This would result in a flow of electron in the channel that increases by due to introduction of the additional charges [27]. In the simulation of GNRFET, the equation can be written in , and coefficients as given by where is the onconductance.
5. Device Simulation
The device performance of GNRFET and MOSFET are compared by evaluating their respective characteristic as shown in Figure 3. The output response of ptype and ntype MOSFETs is superimposed for comparison purposes. Also, the characteristics of ptype and ntype GNRFETs are symmetrical as in a CMOS and thus coincide with each other. Figure 4 illustrated the transfer characteristic of ntype and ptype MOSFET and GNRFET. DIBL and SS are calculated from the curve and are given as The range of the DIBL measurement is taken between V and V and the SS measurement is for the drain current curve at V. As deduced from Figure 3, GNRFET has a lower linear onconductance compared to MOSFET. In addition, GNRFET achieves higher saturation current values than those of MOSFET for most gate voltages.
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As listed in Table 3, the DIBL of MOSFET is better than GNRFET. The subthreshold swing (SS) of both devices is comparable. The ratio of GNRFET is twoorder magnitude lower than that of MOSFET. This is due to a lower linear onconductance limit of a ballistic GNRFET. The onconductance limit, , with zero contact resistance is given by where is the electronic charge and is Planck’s constant. The simulation is carried out using a high gate dielectric constant (high) with high thermal stability. In a practical microfabrication, zirconium dioxide which has high values between 20 and 25 is considered [28].

Note that different values of oxide thickness are being used to obtain almost symmetrical characteristics for both ptype and ntype MOSFET, namely, in the linear region. It is found that when all the transistors adopt equal oxide thickness, the maximum current at V and V differs from one another. The output waveform will not have uniform square wave anymore. The propagation delay, rise time, and fall time will be significantly affected. Thus, they are no longer suitable for logic application due to the mismatch of the ptype and ntype curves at the voltage transfer characteristics.
6. Circuit Design
In this Section, circuit simulation is considered. As part of the circuit design process, parasitic capacitance, namely, load capacitance is determined for an accurate circuit representation. The top diagram in Figure 5 shows a typical arrangement of two inverters in series with . The components of are gatedrain capacitance , , drainbulk capacitance , , and wire capacitance as depicted in the bottom diagram of Figure 5. Note that the term wire capacitance is used interchangeably with interconnect capacitance. Table 4 lists the local, intermediate, and global copper and GNRFET interconnect capacitances for 32 nm, 22 nm, and 14 nm technology process. The finite element method (FEM) charts the pathways in obtaining capacitances as in [29]. The interconnects used in the simulation are considered to be in the intermediate layer [30] and vary from 1 μm to 100 μm in length [31]. It is found that for 0.18 μm technology, average interconnect lengths are considered to be 7 μm per fanout [31]. These interconnect specifications from ITRS 2005 are shown in Table 4.

Table 5 shows the extrapolated interconnect capacitances for the 90 nm, 65 nm, 45 nm, and 16 nm process technologies. The capacitance values of copper and metallic GNR are extrapolated from Figure 6 using a linear function based on the intermediate capacitance in Table 4.

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Table 6 contains the relevant equations for the load and output capacitance for the logic gates.

7. Performance Analysis of Digital Circuit
HSPICE is used to simulate the logic operations of GNRFET and MOSFET. The schematic diagram and inputoutput waveforms of GNRFET and MOSFET NOT, twoinput NAND (NAND2), twoinput NOR (NOR2), threeinput NAND (NAND3), and threeinput NOR (NOR3) gates are delineated in Figures 7, 8, 9, 10, and 11, respectively. All the logic gates consist of 1 μm copper interconnects at the output terminals. In the simulation, the maximum fanin for a gate is limited to 3. Correct logical operations are confirmed from the simulation results as shown in the inputoutput waveforms. Voltage spikes observed are found to be negligible in the output waveform of MOSFET in Figures 7(b)–11(b). The circuit inductance possibly causes spikes that are possible to be compensated by incorporating an onchip decoupling capacitor at the output in parallel. Note that Figures 7–11 are important to calculate the propagation delay which is computed between 50% of the input rising to the 50% of the output rising. Together with the average power consumption, the metric performance of logic gates in term of EDP and PDP is obtained. PDP and EDP parameters are the figure of merit for logic devices. PDP and EDP are given by where is the average power and is the propagation delay. Table 7 lists the and for various logic gates as obtained from the simulation. The PDP and EDP for GNRFET are an order of lower magnitude compared to MOSFET due to smaller and its ultralow during logic operation as revealed in Table 7. GNRFET power consumption is by at least 1 order of magnitude lower than that of a MOSFET.

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Figure 12 depicts the layout for GNRFET NOR2 schematic shown in Figure 9(a). In the topgated design, the GNR is placed under the metal gate and thus hidden from the view. The is supplied to the device through terminals A and B. The verticalinterconnectaccess (via) as labeled in Figure 12 allows a conductive connection between different layers. To realize the number of ptype and ntype transistors as given in Figure 9(a), three and four electrode contacts, respectively, are implemented in the layout. While the series configuration of the ptype transistors requires only three electrode contacts, and four electrode contacts are needed for the ntype transistors connected in parallel.
The Fermi velocity in a GNRFET is distinctly higher than that in a heavily doped MOSFET. Obviously, degenerate statistics is applicable in heavily doped channels. The intrinsic velocity for a nondegenerate lowdoping level is limited to the thermal velocity which is lower than the Fermi velocity in heavily doped semiconductors. The device modeling of GNR adopts similar modeling framework in [17] where we have modified the density of states and quantum conductance limit of a ballistic SWCNT to GNR. The maximum drain current for a monolayer GNRFET is found to be at 19 μA. For CNTFET, the maximum drain current is at 46 μA. Nevertheless, both low dimensional carbon devices outperform silicon MOSFET in term of powerdelayproduct (PDP) and energydelayproduct (EDP) by at least one order of magnitude.
Figure 13 depicts the GNRFET PDP and EDP, respectively, for 0–100 μm copper interconnects in length for various logic gates. Figure 14 shows the MOSFET PDP and EDP, respectively, for 0–100 μm copper interconnect in length for various logic gates. The logic gates with high fanin exhibit increased EDP and PDP as exhibited by these plots. The cutoff frequency at which the current gain is 1 is used to describe the highfrequency performance of a transistor. The current unity gain cutoff frequency of the intrinsic transistor [32, 33] with interconnect capacitance is given by where is the gate capacitance, is the load capacitance, and is the substrate capacitance. Devices with thicker substrate insulator (for instances, 500 nm) and smaller contact area have higher unity cutoff frequency. The unity current gain cutoff frequency for GNRFET circuit model is depicted in Figure 15. The model uses a copper interconnect of the 16 nm, 45 nm, 65 nm, 9 and 0 nm nodes technology. The simulation shows that a 16 nm GNRFET can deliver a unity cutoff frequency of 400 GHz. The interconnect length varies from 0.01 μm to 100 μm. It is found that cutoff frequency is inversely proportional to interconnect length. When the interconnects are longer than 10 μm, the frequency remains the same regardless of the technology nodes. Therefore, it is essential to utilize interconnects as short as possible to tap the highfrequency capability of the CNTFETs [17] and GNRFETs. Our finding is consistent with the stateoftheart graphene transistors that have been shown to reach operating frequencies up to 300 GHz experimentally [34].
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8. Conclusions
Complementary CMOS based on type and type MOSFETs has been at the center stage in industrial environments because of low power consumption. A CMOS circuit draws power from the source only when an inverter is switching from low to high or vice versa. A CMOS inverter is a building block for other gates to build a complete ultralargescaleintegrated (ULSI) ensemble. After the 2010 Nobel Prize awarded to graphene, graphene allotropes have overwhelmed the center stage to capture the advantage of More than Moore’s Era. In fact, Arora and Bhattacharyya [35] show that CNT band structure can be drawn from that of graphene nanolayer with rollover in various chirality directions. GNR [36] offers similar endless opportunities. Considering these noteworthy developments, we believe that graphene allotropes offer distinct advantage over and above the CMOS architecture for a variety of applications in creating sensors, actuators, and transistors for implementation in the ULSI. As graphene allotropes bring to focus the advanced applications, we consider GNR as an example to demonstrate its superiority over the CMOS. Primary reason why graphene is superior to silicon is its intrinsic velocity. The drift in graphene is limited to the Fermi velocity m/s that is 10 times than that of a silicon ( m/s). Saturation velocity limited to the intrinsic velocity determines the highfrequency cutoff of a ULSI circuit. That is the reason that graphenebased electronics will offer unique advantage in highfrequency circuit design. As current saturates, the power in a ULSI circuit is governed by and hence becomes a linear function of voltage, in direct contrast to square law dictated by Ohm’s law. The power consumption will be much lower in a graphene circuit affording the opportunity to lower the scale of the voltage source. Powerfrequency product is a figure of merit in ULSI applications. The paper shows distinct advantages of graphenebased integration in ULSI circuits in designing various Boolean gates. The comparative study stretches the landscape of More than Moore era as traditional scaling reaches its limit. As demonstrated by Greenberg and del Alamo [37], interconnect degrades the device behavior. That is why it is important to include interconnects in the total package of these studies. The rise in the resistance in scaleddown channels also affects the voltage divider and current divider principles, normally based on Ohm’s law. When interconnects are considered in series with the channel, the resistance surges for a smaller length resistor, creating the importance of comprehensive study [38]. Similarly, when parasitic channels are considered in parallel with the conducting channel, the resistance can be higher than what is predicted from Ohm’s law. This rise in resistance can increase the RC time constants as demonstrated in [38, 39]. GNRFET with proper architecture can extend the domain of More than Moore era in meeting the requirements of the future. Shortchannel effects that restrict the silicon technology to reach its full potential are controllable in GNRFET architecture. GNRFET has shown comparable device performance against 16 nm CMOS node. In terms of circuit performance in logic design, the PDP and EPD of GNRFET are distinctly better. The modern adage is “silicon comes from geology, but carbon comes from biology.” This transformation from silicon to carbonbased graphene will usher new era for circuit design based on carbon electronics that is expected to be compatible with bioelements. ULSI designers will greatly benefit from this comparative study as they change their mode of thinking from CMOS to new graphenebased ULSI. We are also expecting that parasitic elements that inhibit the speed of ULSI circuits will pose less of a problem in future architectures based on our findings. The allencompassing landscape covered in this paper will find broader applications benefitting not only the research labs in their characterization and performance evaluation, but also in giving new directions to the industry in product development that will benefit global community.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
Acknowledgments
The authors would like to acknowledge the financial support from UTM GUP Research Grant (Vote nos.: Q.J130000.2523.04H32 and Q.J130000.2623.09J21) and Fundamental Research Grant Scheme (FRGS) (Vote nos.: R.J130000.7823.4F247, R.J130000.7823.4F273, and R.J130000.7823.4F314) of the Ministry of Higher Education (MOHE), Malaysia. Weng Soon Wong thanks Yayasan Sime Darby (YSD) for the scholarship given for his study at the Universiti Teknologi Malaysia (UTM). Vijay K. Arora appreciates the Distinguished Visiting Professorship of the UTM. UTM Research Management Centre (RMC) provided excellent support conduciveness to the research environment needed to complete project of this magnitude with personnel of farreaching background.
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Copyright
Copyright © 2014 Huei Chaeng Chin et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.