Metal-Insulator Phase Transition in Quasi-One-Dimensional VO₂ Structures

Figure 11

(a) A schematic illustration and a SEM image of a thermal memory device with an individual VO₂ nanobeam connecting the input terminal and output terminal (upper panels). High/low (HI/LO) temperature states over 150 repeated cycles by using a one-second heating pulse and a one-second cooling pulse at the input terminal under a voltage bias of 0.04 V (lower panel). The inset shows the process of Write HI-Read-Write LO-Read over three cycles. (b) The resistance (R)-voltage (V) hysteresis curve (upper left panel). Insets show the crystal structures of VO₂ with a monoclinic phase (VO₂(M)) and a rutile phase (VO₂(R)). A schematic of the memory device based on a single VO₂ nanowire showing the gradual change of metallic/insulating phases inside the nanowire at different points marked in the R-V curve (I, II, III, and IV in the upper right panel). Nonvolatile switching property of a single VO₂ nanowire memory device (lower panel). Panels (a) and (b) adapted with permission from [43] and [44], respectively.

(a)

(b)