Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

<div>Graph of <svg height="11.5877pt" id="M22" style="vertical-align:-3.13769pt" version="1.1" viewbox="0 -8.45001 15.4713 11.5877" width="15.4713pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M418 650H141L133 618C225 611 232 604 218 531L141 120C126 45 119 37 33 32L24 0H301L308 32C220 37 214 44 227 120L305 531C319 605 325 611 411 618L418 650Z" id="g50-74"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="442" vert-adv-y="442"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,4.797,3.001)"><path d="M43 650V622C120 616 128 612 128 526V124C128 39 120 33 34 27V0H270C392 0 492 25 567 83C643 141 690 230 690 350C690 444 655 517 605 565C543 625 450 650 323 650H43ZM213 547C213 587 217 598 226 604C236 612 262 617 304 617C371 617 429 604 474 576C554 529 592 439 592 336C592 176 505 36 319 36C246 36 213 55 213 131V547Z" id="g190-69"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="735" vert-adv-y="735"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,11.486,3.001)"><path d="M409 504C401 567 396 607 392 642C354 654 312 665 266 665C137 665 60 583 60 487C60 374 161 325 225 290C300 250 355 215 355 141C355 68 311 21 235 21C131 21 86 122 71 183L41 176C48 128 61 42 68 21C78 16 93 8 118 0C142 -7 175 -15 216 -15C349 -15 438 69 438 174C438 287 344 333 265 374C186 414 138 449 138 522C138 576 172 631 249 631C336 631 363 562 380 499L409 504Z" id="g190-84"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="474" vert-adv-y="474"></glyph.data></g></svg> versus <svg height="11.5877pt" id="M23" style="vertical-align:-3.13769pt" version="1.1" viewbox="0 -8.45001 18.1233 11.5877" width="18.1233pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M735 650H491L482 618L516 614C568 608 571 595 541 535L299 115H297L196 559C187 600 195 608 238 614L265 618L275 650H26L18 618C79 611 98 605 115 527L234 -9H272C389 197 542 449 591 523C647 608 656 612 726 618L735 650Z" id="g50-87"></path><glyph.data ascent="3443" descent="-2856" horiz-adv-x="747" vert-adv-y="747"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,7.449,3.001)"><path d="M43 650V622C120 616 128 612 128 526V124C128 39 120 33 34 27V0H270C392 0 492 25 567 83C643 141 690 230 690 350C690 444 655 517 605 565C543 625 450 650 323 650H43ZM213 547C213 587 217 598 226 604C236 612 262 617 304 617C371 617 429 604 474 576C554 529 592 439 592 336C592 176 505 36 319 36C246 36 213 55 213 131V547Z" id="g190-69"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="735" vert-adv-y="735"></glyph.data></g><g transform="matrix(.0091,0,0,-0.0091,14.138,3.001)"><path d="M409 504C401 567 396 607 392 642C354 654 312 665 266 665C137 665 60 583 60 487C60 374 161 325 225 290C300 250 355 215 355 141C355 68 311 21 235 21C131 21 86 122 71 183L41 176C48 128 61 42 68 21C78 16 93 8 118 0C142 -7 175 -15 216 -15C349 -15 438 69 438 174C438 287 344 333 265 374C186 414 138 449 138 522C138 576 172 631 249 631C336 631 363 562 380 499L409 504Z" id="g190-84"></path><glyph.data ascent="989" descent="-360" horiz-adv-x="474" vert-adv-y="474"></glyph.data></g></svg> of FinFET.</div>

Journal of Nanomaterials

fig7

Figure 7

Figure 7: Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology 