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Journal of Nanomaterials
Volume 2015 (2015), Article ID 782786, 6 pages
http://dx.doi.org/10.1155/2015/782786
Research Article

Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

Department of Electronic Engineering, National United University, No. 1 Lienda, Miaoli 36003, Taiwan

Received 1 September 2015; Accepted 23 November 2015

Academic Editor: Christian Brosseau

Copyright © 2015 Yu-Hsien Lin and Jay-Chi Chou. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using different high-k gate dielectric materials such as silicon nitride (Si3N4) and aluminum oxide (Al2O3) at low temperature process (<300°C) and compared them with low temperature silicon dioxide (SiO2). The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

1. Introduction

The emergence of transparent thin film transistors (TTFTs) has enabled satisfying consumer requirements for electronic products. Because of their numerous advantages, TTFTs are anticipated to become the next generation of transistor materials. Among the various types of transparent thin film materials currently in use, indium gallium zinc oxide (IGZO) is extremely promising [16]. IGZO is highly flexible and has a carrier mobility of up to 10 cm2·V−1·s−1 [7]. These properties have had a considerable impact on advancing the applications of TTFTs.

The energy gap of IGZO approximates 3.1 eV [8]. The transmittance rate of IGZO can reach up to 90%, exceeding 80% under certain annealing conditions [9]. The main structure of IGZO is ZnO doped with In3+ and Ga3+; trivalent indium and gallium can be used as replacements for divalent zinc to provide additional cations for enhancing carrier mobility. According to previous studies, doping IGZO with indium enhances its carrier mobility, whereas including gallium reduces its carrier mobility. Including indium provides extra cations; In–O has a weak bond that can be broken easily to produce oxygen vacancies. Although including gallium reduces carrier mobility, it does not have a marked effect on distorting the original lattice because the bond length of Ga–O approximates to that of Zn–O and Zn2+ and Ga3+ have a nearly identical radius. The bonding of Ga–O is far stronger than those of In–O and Zn–O; thus, oxygen vacancies can be inhibited by utilizing the Ga–O bond. Because of these properties, fabricating IGZO thin films does not introduce excessive defects and cause deterioration in their electrical property. The doping ratio of indium, gallium, and zinc can influence the crystal structure and carrier mobility. Currently, IGZO doped with indium : gallium : zinc : oxygen at a ratio of 1 : 1 : 1 : 4 has been used in many studies [1013].

Nowadays, many semiconductor manufacture companies are currently using the high-k dielectric materials as replacement materials for SiO2 as the gate dielectric materials for complementary metal-oxide-semiconductor (CMOS) process [1416]. The required properties of gate dielectrics need considering the key guidelines such as high dielectric constant, proper conduction and valence-band offset, thermodynamic stability, interface quality, process compatibility, and device reliability. With high-k gate dielectric materials, the high drive currents with large capacitance, low leakage current, and low operation voltage could be achieved for CMOS devices.

In this paper, we integrate the a-IGZO thin film transistors by using different high-k gate dielectric materials and research the interface between the high-k dielectric thin film/IGZO interfaces through the thermal annealing. We use the low temperature PECVD SiO2, PECVD Si3N4, and room temperature E-gun Al2O3 thin film for the gate dielectric material. The effect of temperature treatment on a-IGZO TFTs was studied due to the interface reaction. The thermal budget is crucial and will influence the device characteristics such as subthreshold swing (SS), ratio, carrier mobility, and stress characteristics. Moreover, the stress effect of the IGZO device was explained by using energy band diagram for the electrical characteristics of a-IGZO TFTs.

2. Fabrication

The a-IGZO TFTs with different high-k dielectric were fabricated by using N+-type wafers and a bottom gate structure, as shown in Figure 1. By using the bottom structure, we could focus on the interface between the high-k dielectric thin film/IGZO interfaces through thermal annealing [17, 18]. First, after the RCA clean, three different gate dielectric materials were deposited with thickness of 10 nm. The splits were SiO2 by using PECVD method at 300°C, Si3N4 by using PECVD method at 300°C, and Al2O3 by using E-gun method at room temperature, respectively. For comparison with above layers, we also use furnace SiO2 at 950°C as optimized gate oxide to eliminate the interface effect. Then, a 30 nm a-IGZO layer was deposited using sputtering method with IGZO4 targets (In : Ga : Zn : O ratio of 1 : 1 : 1 : 4) in ambient oxygen gas (O2). The cosputtering process was performed at 4 × 10−3 Torr in room temperature with precursors of O2 (6 sccm) and Ar (24 sccm), and the DC sputter power was set at 150 W. After active region patterning, 30 nm titanium (Ti) thin film was deposited and used for source and drain electrodes, using the E-gun method at room temperature. After source/drain patterning, postannealing treatment was performed for 30 minutes at temperature of 200°C. The dimensions of the devices were length/width dimensions of 200/1000 μm.

Figure 1: Cross section of the fabricated bottom-gate a-IGZO TFTs using high-k materials.

3. Results and Discussion

The basic curve of the a-IGZO TFTs using high-k materials is shown in Figure 2(a). For the measurement, the gate voltage varied from −5 to 5 V and the drain voltage was 1 V. Figure 2(b) shows the curve of the a-IGZO TFTs, and the drain voltage varied from 0 to 10 V and the gate voltages were 0, 2.5, and 5 V. We could observe that the Si3N4 sample has higher , lower , higher ratio, and high mobility due to the higher dielectric constant compared to SiO2 sample and Al2O3 sample. However, the SiO2 sample has good SS compared to others because of good interface with IGZO. The a-IGZO TFTs with Si3N4 gate dielectric exhibited superior characteristics. The summary table of the measurement data is shown in Table 1.

Table 1: The summary table for the a-IGZO TFTs using high-k materials.
Figure 2: (a) curve of the a-IGZO TFTs using high-k materials. (b) curve of the a-IGZO TFTs using high-k materials.

As shown in Figures 3(a)3(d), following a gate voltage stress of −5 V, of PECVD SiO2 and E-gun Al2O3 sample increased as the stress time lengthened, and slightly shifted to the right; by contrast, for the PECVD Si3N4 sample, shifted to the left. Following a gate voltage stress of +5 V, PECVD SiO2 and E-gun Al2O3 sample have deterioration just like device on, and the E-gun Al2O3 sample deteriorated more apparently than did the PECVD SiO2 sample. By contrast, for the PECVD Si3N4 sample, shifted to the right as the stress time increased and did not deteriorate. To determine the problem causing the observed phenomena, SiO2 gate-insulating layer with the same thickness was developed using a horizontal furnace tube through the dry oxide method at 950°C, as shown in Figure 3(d). The dry oxide formed using horizontal furnace was used as the control sample. The results showed that, following numerous sweeps of negative gate voltage stress, the components exhibited minimal change in characteristics. Following the positive voltage stress tests, neither shifted to the left nor deteriorated. These results accord with the trend observed for Si3N4 sample and the characteristics of positive gate voltage stress [1921]. This phenomenon is attributed to the interface effect between the gate-insulating layer and the IGZO. Thus, the problem was related to changes in the interface after stressing. Moreover, we could also calculate the interface trap density () by the difference of the subthreshold swing (SS) between the original sample and stressed sample. The interface trap density () was calculated based on the equation , where is the depletion capacitance density of IGZO and (= ) is the capacitance density from charged interface traps [22, 23]. By neglecting , for the original PECVD SiO2 sample, PECVD Si3N4 sample, and E-gun Al2O3 sample are 2.9 × 1012, 6.6 × 1012, and 5.3 × 1012 cm−2 eV−1, respectively. After voltage positive gate voltage stress for 10 seconds, for the stressed PECVD SiO2 sample, PECVD Si3N4 sample, and E-gun Al2O3 sample are 3.5 × 1012, 6.9 × 1012, and 7.1 × 1012 cm−2 eV−1, respectively. For the comparison with the original and the stressed device, the degradation ratios of the PECVD SiO2 sample, PECVD Si3N4 sample, and E-gun Al2O3 sample are 20.6%, 4.5%, and 34.0%, respectively. As a result, the IGZO TFTs with Si3N4 gate dielectric have the lowest after stressing.

Figure 3: Various insulating layers with ±5 V stress for comparison: (a) PECVD SiO2, (b) E-gun Al2O3, (c) PECVD Si3N4, and (d) SiO2 control sample of furnace process.

According to the experimental results, the type of gate oxide layer had a substantial influence on the performance of the IGZO thin film transistor (TFT). As indicated in previous studies, stress-induced component characteristics are analogous to those of PECVD Si3N4 sample and dry oxide sample (control), demonstrating shifts in their . Such shift is attributed to the donor-like trap at the interface between the insulating layer and IGZO layer. As shown in Figure 4, generally, a donor-like carrier located below the Fermi level is considered as a neutral carrier, whereas one located above the Fermi level is considered as a positively charged carrier. When positive voltage stress is applied to a gate, the conduction band bends downward because of the electric field, reducing the distance between the contact surface and the Fermi level. This behavior suggests that the number of positively charged donor-like carriers between the conduction band and Fermi level decreases, increasing the number of neutral carriers. If the conduction band that bends because of stress is measured before it returns to its unbent state, then becomes large and shifts to the right because of the decrease in the number of positive charges; consequently, the conduction band cannot attract more electrons and higher voltage is required to obtain the same number of electrons. Conversely, when negative voltage stress is applied to a gate, the conduction band bends upward, the number of positively charged donor-like carriers increases, and the number of neutral carriers decreases, thus diminishing and shifting to the left [21].

Figure 4: Mechanisms of positive and negative gate voltage stress.

In low temperature processes, except for PECVD Si3N4 sample in the gate-insulating layer, the channels of other insulting layer materials cannot close under positive voltage stress. Disregarding the fact that this phenomenon is a result of current induced by the collapse of the insulating layer, this study considered interface-related problems. Some IGZO carriers are provided by oxygen vacancies; therefore, in this study, the responses of the interface between the IGZO and insulating layer materials were examined to determine whether the IGZO and the insulating layer materials competed for oxygen and whether the IGZO produces extra oxygen vacancies. The standard heat of formation indicates that Al2O3 < SiO2 < Si3N4 [24, 25]. As shown in Table 2, the forming of negative heat indicates that a chemical compound is stable, the probability of interface formation is large, and the chemical compounds in IGZO compete for oxygen (according to the table, the heat formation in ZnO is close to zero; thus, the oxygen in ZnO is most likely occupied). The behaviors of the SiO2 control sample formed through using a horizontal furnace tube and SiO2 sample developed through plasma-enhanced chemical vapor deposition have resulted from oxide layer defects near the interface.

Table 2: Gate-insulating layer and heat formation in IGZO compounds.

According to the aforementioned hypothesis, the following explanations for deterioration were proposed. When a gate is influenced by positive voltage stress, accumulated IGZO electrons may be trapped in the interface or in the oxide layer defects. These trapped electrons generate electric fields even when voltage stress is not applied. Accordingly, the conduction band can bend downward without positive voltage stress causing electrons to accumulate. If the insulating layer accepts oxygen in the IGZO, then additional oxygen vacancies and electrons are produced. Once additional electrons under positive voltage stress are trapped in the interface or in the oxide layer defects, the conduction band is severely bent downward and a considerable number of electrons accumulate. Consequently, the component channels cannot close and the band diagram was shown in Figure 5.

Figure 5: Deterioration of components after applying positive gate voltage stress.

4. Conclusion

In this paper, we demonstrate the low temperature IGZO TFT device with different high-k gate dielectric materials such as PECVD Si3N4 (300°C) and E-gun Al2O3 (room temperature) and they are compared to the PECVD SiO4 (300°C). The PECVD Si3N4 sample could yield high mobility, high ratio, high , low , and better stress effect than others. The stability between the high-k dielectric thin film and IGZO thin film caused interface roughness due to the heat formation difference during temperature annealing. The charge is generated in the interface and results in shift during stress. The stress effect could be explained in the interface by charge band diagram. As a result, the IGZO TFTs with Si3N4 gate dielectric exhibit good characteristics with acceptable reliability in the low temperature process.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

This study was sponsored by the Ministry of Science and Technology, Taiwan, under Contract no. 104-2221-E-239-017. The technical support of the National Nano Device Laboratories is also greatly appreciated.

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