Abstract
Carbon nanotube field-effect transistor (CNTFET) is a good option to replace silicon for low power consumption application. Recent research shows that CN-FET thermal and electrical properties alter with length, diameter, and gate parameters. Optimization of CNTFET design parameters helps control some of the factors. Double gate and cylindrical gate layouts are introduced to overcome these facts. Carbon nanotubes have an intercapacitance between them that increases as their diameter increases. Total capacitance and inductance of CNTFETs increase with nanotube count. In order to reduce the voltage drop between semiconducting and metallic terminals, the diameter and pitch must be raised. This study employs response surface methodology and ANOVA technique that were used to optimize CNTFET process parameters. Thickness, voltage, delay, and power were all considered. The most affecting parameter was investigated.
1. Introduction
CNTFETs have been proposed as CMOS device changeover. It only needs to be combined with high-k dielectric CMOS technology to have other device characteristics. CNTFET is a three-terminal device made up of semiconducting nanotubes that connect the source and drain and act as a carrier channel. It can be electrostatically connected via the third contact (gate). Ding et al. investigated an FDSOI nMOSFET manufactured using a similar technique under the same irradiation environment and bias during irradiation comparison. They also explained how to compare experimental and simulated curves for a fresh TFET with a simulated curve for a TFET irradiated [1]. Sanchez Esqueda et al. demonstrated the development of radiation-induced oxide trapped charge and the production of interface traps in bulk MOSFETs, SOI MOSFETs, and SOI MOSFETs. They also brilliantly explained that the minimum data retention voltage (DRV) as a function of PMOS stress-induced trap building got results from simulations before and after including total ionizing dose (TID) effects as edge leakage in NMOS devices [2]. Ning and Zhang compared the off-state leakage current for I/O FB and TB devices under ON and OFF bias settings. They also looked at the back-gate threshold voltage shift for core FB and TB devices when the bias was turned off. For the core FB and TB devices, they specifically indicated simulated body potential with the channel length (horizontal direction) at the middle depth of the body area and simulated electric field strength (EY) along with the depth (vertical direction) at the middle depth of the BOX under OFF bias condition [3].
Cress et al. described ionizing dose-hardened CNT transistors with silicon oxynitride gate dielectrics. The irradiation impact causes substantial error operation in the CNTFET integrated circuit. The threshold voltage shift also appears to confirm the device structure in a radiation environment [4]. A CNT network between the source and drain electrodes was irradiated with gamma rays. They exhibited the device’s I-V characteristics before and after 50 kGy irradiation, with VGS ranging from -20 to +20 V at and the averaged Vth dose-dependence. The averaged (difference between before and 10 hours after irradiation) dose-dependency ranges from 5 to 50 kGy [5]. It was clearly stated by Avouris et al. Carbon electronics has been identified as a promising candidate for the next generation of electronics and nanodevices [6]. Tang et al. demonstrated that nanotube-based dosimeters could detect ionizing radiation like 6 MV therapeutic X-rays with greater sensitivity than MOSFET devices. They concluded that the gadget retained its form and functionality after radiation exposure and that the nanotubes were not damaged [7].
Schrimpf et al. convincingly demonstrated graphs of gate voltage vs. drain current for various relationships and concluded that total-ionizing-dose effects were, on average, less severe for substantially scalable technologies as opposed to preceding methods [8]. Cress et al. distinguished the transfer properties of a back-gated graphene-FET with incremental total ionizing radiation, the same device after 15 minutes of air exposure, and the same device with an additional total ionizing dose (TID). They also highlighted field-effect mobility as a function of TID for a graphene-FET irradiated in vacuum and air and the least amount conductivity for transfer characteristics estimated in a vacuum. The graph drain current vs. gate voltage also clearly demonstrated graphene transistors exposed to varied total ionizing doses [9]. Zhang et al. precisely described how CNTFET devices respond to electrical stress and cycling. They also demonstrated the current drain ID as a function of gate voltage VG for a variety of total doses using an irradiation gate bias of +10 V, as well as the postirradiation annealing time following irradiation to a whole dosage of 1 Mrad (SiO2), likewise with a functional gate bias of +10 V [10].
Baligidada et al. undoubtedly investigated the effects of restrictions such as the thickness of layer, power derived from the heater, and heater supply rate on properties like storage modulus and loss modulus of several test samples. They also recommended using CCD-RSM to optimize process settings for better mechanical qualities of polyamide parts [11]. Yang and Tarng used orthogonal array, signal-to-noise ratio, and ANOVA to optimize cutting parameters for turning operations and concluded that rotating improved tool life and surface roughness. Tool life and surface roughness were about 225% ideal cutting parameters [12]. Lipin and Govindan briefly described Taguchi methods for designing experiments and investigating records for optimizing processing conditions utilizing orthogonal arrays. They showed the influence of factors on MRR and surface roughness. They concluded that the Taguchi approach could improve tool life, surface roughness, cutting force, and overall productivity [13].
dos Santos et al. demonstrated that the independent variables’ uncoded and coded levels were related to synthesis. The independent variables and experimental values of response variables for the central composite also demonstrated that design was connected to synthesis. They stated that they performed ANOVA on the degree of the variable response of quarterization, intrinsic viscosity, and reaction yield correlated to the synthesis of N-(2-hydroxy)-propyl-3-trimethylammonium chitosan chloride, as well as on the temperatures and corresponding weight losses related to the thermal degradation of chitosan and samples, among other things [14]. Tsao and colleagues described the primary elements experimentally impacting hole quality in drilling, such as cutting speed, temperature, feed rate, and geometrical parameters, and the influence of manipulating the cutting conditions and temperature on the tool life [15].
2. Methods and Methodology
Response surface methodology (RSM) is a collection of mathematics and arithmetic tools for assembling experimental representations. The goal of a suspicious proposal of experiments is to maximize a response such as an output variable subjective by numerous self-governing variables such as input variables. A series of tests are conducted in which the input variables are changed to identify the motivation for changes in the output response. In this configuration, the input parameters were thickness and voltage, whereas the desired output parameters were delay and power. Table 1 displays the various thickness and voltage input parameter ranges. The related delay and power values of thickness and voltage for CNTFETs are shown in Table 2.
3. Result and Discussion
The findings of the experiment were analysed for CNTFET based on the design of the experiment. Figure 1 depicts the main effect plot for means, highlighting the relationship between the mean of the mean and the thickness of the CNTFET and the link between the mean of the mean and the voltage utilized for the same. The mean was directly proportional to voltage and inversely proportional to thickness based on this indication [16]. The preferred thickness and voltage for the mean are 22 nm and 0.4 V, respectively, for the mean. Figure 2 shows the SN ratio’s primary effects plot about thickness and voltage for the SN ratio. According to this graphical representation, the mean of the SN ratio fell in response to an increase in voltage. The SN ratio values, on the other hand, grow as the thickness of the CNTFET is raised. As a result, the almost optimal thickness and voltage were 20 nm and 0.6 V, respectively, when measured in the SN ratio.
Figure 3 depicts the responses of the SN ratio and residual values. Residual values gradually increase from negative to positive. According to the graph, the response for this configuration was close to the SN ratio in percentage terms. The solid colour line displayed the average value.
The graphical representation of residuals and fits for SN ratios is shown in Figure 4. The fitted values were listed horizontally, whereas the residual values were listed vertically. In response to SN ratios, residual values are arranged between -0.3 and 0.2, and fitted values are in the negative range.
Figure 5 shows various observation order for the residual values. There were less than 50% of the values in this graphical representation that was negative indicators, and more than 50% of the values in this graphical representation were positive indications. The options of rising and fall were accessible; however, the residuals were almost identical in the intermediate observation.
The normal probability plot about the residuals is depicted in Figure 6. The block line represented the average value, and the residual values were roughly equal to the average values depicted in the image.
The residual values to the fitted values with matching mean values are shown in Figure 7. The residual was in the range of -0.10 to 0.15. The majority of the fitted values were negative, accounting for almost 65% of the total, with the remaining positive replies.
An illustration of the residual about an order for means is depicted in Figure 8 in graphical form. There were residual values that were predominantly negative, accounting for roughly sixty-five percent of the total. However, the remaining thirty-five percent of respondents gave a positive reaction.
Figure 9 depicts the relationship between residuals for standard deviations and probability. This approach yielded results such as all values being quite close to the average. Figure 10 also depicts the responses of standard deviations concerning residuals in the range of -0.25 to 0.21.
Similarly, Figure 10 depicts residuals versus fits for standard deviations. 65% of respondents gave a good answer, while the remaining 35% gave a negative response. Standard deviations concerning residuals were in the range of -0.25 to 0.2.
Figure 11 depicts residual values about fitted values related to standard deviations. According to this graphical representation, the residual values ranged from -0.25 to 0.2, and the fitted values ranged from 1.85 to 2.6. Figure 12 depicts a contour plot of power vs. thickness and voltage, with significant colour changes. When the thickness is greater than 30 nm, the voltage exceeds 0.3 V, and power increases.
Figure 13 depicts the contour plot of delay vs. thickness and voltage using various colour differences. When the thickness value is increased (more than 17 nm) and the minimum voltage is close to 0.2 to 0.3, the delay decreases. Figure 14 shows a surface plot of power vs. thickness and voltage in three dimensions. Thickness was mentioned in the -axis, power in the -axis, and voltage in the -axis. Powers increase in response to a decrease in thickness as well as an increase in voltage. Figure 15 depicts a surface plot representation of delay vs. thickness and voltage. Thickness was mentioned in the -axis, latency in the -axis, and voltage in the -axis. With the increasing thickness and decreasing voltage, the delay decreased.
4. Conclusion
An examination of all of the parameters used in CNTFET optimization has been performed. The mean of the SN ratio fell in response to an increase in voltage. Optimal thickness and voltage were measured as 20 nm and 0.6 V. Standard deviations were observed in the range of -0.25 to 0.21. The thickness of the CNTFET is the most influential parameter to improve the results. The ideal thickness and voltage are 22 nm and 0.4 V resulting in the maximum power and lowest delay.
Data Availability
The data used to support the findings of this study are included in the article. Should further data or information be required, these are available from the corresponding author upon request.
Disclosure
The work was performed as a part of the Employment of Mettu University, Ethiopia.
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.
Acknowledgments
The authors thank KPR Institute of Engineering and Technology and Vellore Institute of Technology, Chennai, for the technical assistance. The authors appreciate the supports from Mettu University, Ethiopia.