Journal of Nanotechnology / 2012 / Article / Fig 3

Review Article

Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications

Figure 3

SEM pictures at different stages of device fabrication. (a) Vertical nanowire with diameter ~20 nm; (b) after gate patterning by lithography but before exposing the drain (the tip of the pillar) of the transistor; (c) after the drain (pillar tip) is exposed, ready for taking metal contacts, (d) vertical nanowire arrays with pitch of 500 nm. Nanowires are 1 μm tall with a diameter of ~20 nm. (Reprinted with permission from [15]. [2008] IEEE.)
492121.fig.003a
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492121.fig.003b
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492121.fig.003c
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