Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Table 1

Node’s parameters.

	3	2	1	2	1	2	3	1	1	3	3	1	5	4	2
	6	4	2	4	2	4	7	2	2	7	6	2	10	9	5
	2	1	2	1	1	2	2	1	1	3	3	1	4	4	5
	0.5	0.25	0.5	0.25	0.25	0.5	0.5	0.25	0.25	1	1	0.25	1	1.5	2