Research Article
Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System
Table 8
Design result provided by Tabu Search algorithm.
| 8-point DCT | Best partition | Hardware | 13 operations of (×) | 0 operations of (+) | Software | 3 operations of (×) | 26 operations of (+) | Total power consumed (mW) | 86.8 | The system’s latency (ns) | 493 |
| 16-point DCT | Best partition | Hardware | 40 operations of (×) | 44 operations of (+) | Software | 88 operations of (×) | 52 operations of (+) | Total power consumed (mW) | 393.712 | The system’s latency (ns) | 3776 |
| H.264 | Total power consumed (W) | 5.276 | The system’s latency (ns) | 1990 |
|
|