Research Article

Power and Execution Time Optimization through Hardware Software Partitioning Algorithm for Core Based Embedded System

Table 8

Design result provided by Tabu Search algorithm.

8-point DCTBest partitionHardware13 operations of (×)0 operations of (+)
Software3 operations of (×)26 operations of (+)
Total power consumed (mW)86.8
The system’s latency (ns)493

16-point DCTBest partitionHardware40 operations of (×)44 operations of (+)
Software88 operations of (×)52 operations of (+)
Total power consumed (mW)393.712
The system’s latency (ns)3776

H.264Total power consumed (W)5.276
The system’s latency (ns)1990