A Controllable Constant Power Generator in 0.35 μm CMOS Technology for Thermal-Based Sensor Applications

Abstract

A CMOS controllable constant power generator based on multiplier/divider circuit is presented. It generates constant power for a wide range of the resistive loads. For the generated power of 5 mW, and the resistance range from 0.5 kΩ to 1.5 kΩ, the relative error of dissipated power is less than 0.6%. For single supply voltage of 5 V, presented controllable constant power generator generates power from 0.5 mW to 7.8 mW, for the load resistance dynamic range from 3 up to 15, while the relative error of generated power is less than 2%. The frequency bandwidth of the proposed design is up to 5 MHz. Through the detailed analysis of the loop gain, it is shown that the circuit has no stability problems.

1. Introduction

The circuit which generates constant power for variable resistive loads finds application in various types of thermal-based sensors, such as mass flow meters, anemometers [1], AC power meters, gas monitoring [2, 3], plant water status monitoring [4], seepage meters [5], and other flowmeters intended for very slow fluids. Thermal-based flow sensors are very attractive because of their simple construction. They basically consist of constant power generator and sensing element. The surrounding fluid transfers heat to/from sensing element depending on its flow rate. As the temperature of the sensing element is changed, its resistance is changed, and the constant power generator changes the voltage drop across the sensing element to keep constant power. Measuring the voltage change across the sensing element, it is possible to extract the information about the fluid flow rate. So, the quality of the constant power generator as a part of the thermal-based sensor is very important. Controllable constant power generator is the circuit which generates constant power dissipation over a range of resistive loads. The control of the generated power is provided by control voltage or control current. The range of resistive loads has to be as large as possible for the particular generated power. In that sense, the quality of constant power generators is determined by the load resistance dynamic range, defined as the ratio of the largest load resistance to the smallest load resistance (R_Lmax/R_Lmin), for the particular value of dissipated power. The other important characteristic of the constant power generator is the value of generated power for a given load resistance, depending on specific application. The relative error of generated power over the range of load resistance is the key quality parameter of the constant power generator. Low-supply voltage of constant power generator is critical for many applications as a consequence of the general trend in electronics. The ratio of the largest voltage drop across the resistive load and supply voltage (V_Lmax/V_DD) can be used as a quality indicator of constant power generators. One of the main problems in constant power generator design is its stability caused by feedback loops.

There are several designs of constant power generators, developed mostly in BiCMOS and bipolar technologies. A CMOS controllable constant power generator based on the resistive mirror [1] has the range of generated power from 0.48 mW to 10.8 mW, and the load resistance dynamic range up to 28, with the relative error of generated power less than 2.2% and the supply voltage of 10 V. The constant power generator presented in [1] uses four operational amplifiers OP97 which are designed in a complementary bipolar technology, while the rest of the circuit is realized using n-channel MOSFETs. Hence, the circuit [1] can be considered as a BiCMOS technology design. The controllable constant power generator [3], based on CMOS translinear loop, has a load resistance range from 470 Ω to 1.47 kΩ and is able to generate power up to 11 mW, with the supply voltage of ±5 V and the relative error of generated power up to 3%. The circuit presented in [3] uses off-chip operational amplifier LM301 designed in a complementary bipolar technology, while the rest of the circuit is realized in a CMOS technology. Hence, the circuit [3] can be considered as a BiCMOS technology design. Controllable constant power generator [4–6] can change the dissipated power by a factor of 1 : 1000, using the log-antilog circuit with bipolar junction transistors. This controllable constant power generator uses eight OPA4227 operational amplifiers designed in a complementary bipolar technology. Consequently, the circuit [4–6] can be considered as a bipolar technology design. The controllable constant power generator [7] in BiCMOS technology achieves load resistance range of 1 : 50, with generated power up to 100 mW. The microcontroller-based solution [9] can achieve large resistance dynamic range and large power dynamic range, but at the price of reduced frequency bandwidth. The CMOS design proposed in [10] for small variations of the resistive load has a large relative error of the generated power.

Taking into account that the existing designs of controllable constant power generators are designed mostly in BiCMOS and bipolar technologies and that CMOS technology is the most popular and the cheapest technology so far, the goal of this work is the design of fully integrated controllable constant power generator in a pure CMOS technology. This paper presents controllable constant power generator in 0.35 μm CMOS technology based on current-mode multiplier/divider circuit [8]. The generated power can be adjusted by two control currents which are the input currents of the multiplier/divider circuit. Through the detailed analysis and simulations, it is shown that proposed design is able to generate constant power over a large range of the load resistance. The mathematical model for the loop gain of the controllable constant power generator shows that circuit has no stability problems for a wide range of resistance for the particular generated power. The influence of the process parameter variations and the temperature variations to the proposed design is also analyzed.

2. Circuit Description

2.1. Basic Principle

The main purpose of the constant power generator is to maintain the constant power dissipation across the resistive load: where P_L is the generated power across the resistive load, I_L is the current flowing through the resistive load, and V_L is the voltage across the resistive load. Generated power has to be independent of the load resistance. Also, it is desirable to have the possibility to control generated power easily.

The basic principle of the controllable constant power generator with a novel method for achieving a constant power dissipated on the resistive load is shown in Figure 1. It consists of multiplier/divider circuit, second generation current conveyor (CCII), load resistor R_L, reference resistor R_REF, and two DC current sources I₁ and I₂. The output current I_L of the multiplier/divider circuit is flowing through the resistive load R_L. The voltage V_L across the resistive load is transferred via CCII to the resistor R_REF. So, the output current I₃ of the CCII is given by

Figure 1 

The principle of operation of the proposed controllable constant power generator.

On the other hand, the output current of the multiplier/divider circuit is given by

So, the generated power P_L can be expressed as

The generated power is independent of the load resistance R_L and can easily be adjusted by changing control currents I₁ and/or I₂.

2.2. Complete Circuit Schematic

The multiplier/divider circuit [8] is shown in Figure 2. It is based on the CMOS translinear principle. The circuit can be divided into two parts. The first part gives the current which is proportional to the square root of the product of two input currents (geometric mean) at its output. The second stage performs squarer/divider operation. The MOSFETs M₁, M₂, M₃, M₄, M_1a, M_2a, M_3a, and M_4a have long enough channels of 3 μm, so the channel length modulation effect can be neglected in the analysis. Assuming a good enough matching of MOSFETs forming the translinear loops (V_t1 = V_t2 = V_t3 = V_t4, V_t1a = V_t2a = V_t3a = V_t4a, β₁ = β₂ = β₃ = β₄, and β_1a = β_2a = β_3a = β_4a) and a simple quadratic model for the drain current of the MOSFET operated in the saturated region, it can be shown [8] that the output current I_L of the multiplier/divider circuit is given by

Figure 2 

Multiplier/divider circuit schematic [8].

The second-order effects of the multiplier/divider circuits, such as channel length modulation effect and the threshold voltage mismatching effect, are analyzed in [8]. It is stated that the channel length modulation effect can be neglected for the long channel MOSFETs. On the other hand, the threshold voltage mismatching effect could affect the performances of the multiplier or divider circuit, assuming that the multiplier and divider are analyzed separately. On the other hand, if the multiplier and divider are used simultaneously within the multiplier/divider circuit, the threshold voltage mismatching effect is compensated [8]. The body effect of the n-channel MOSFETs in a real n-well CMOS implementation can be solved using n-channel MOSFETs with their own p-wells assuming a twin well technology.

The complete circuit schematic of the proposed controllable constant power generator with a novel method for achieving a constant power dissipated on the resistive load is shown in Figure 3. The output current of the multiplier/divider circuit is flowing through the resistive load R_L. The current I₃ is obtained as the output current of the CCII. The voltage V_L across the resistive load R_L is transferred via input stage of the CCII, so the current at terminal X of this CCII is V_L/R_REF. The differential input stage of the CCII is formed by the MOSFETs M₁₂ and M₁₃, with the active cascoded load (MOSFETs M₁₄, M₁₅, M₁₆, and M₁₇). The differential input stage is biased by MOSFET M₁₁ and biasing voltage V_B3. The output current is transferred by the two output cascoded current mirror (MOSFETs M₁₈, M₁₉, M₂₀, M₂₁, M₂₂, and M₂₃). So, the current at the output of the CCII is I₃ = V_L/R_REF. To change the direction of the current I₃, the wide-swing current mirror is used. This current mirror consists of MOSFETs M₂₄, M₂₅, M₂₆, and M₂₇ and biasing voltage V_B4. The current I_L flowing through the resistive load R_L is mirrored by the current mirror formed by the MOSFETs M_6a, M_8a, M₉, and M₁₀. The current mirror formed by the MOSFETs M₂₈, M₂₉, M₃₀, and M₃₁ is used to sum currents I₃ and I_L and to divide the sum of the currents by four. In that aim, the channel widths of the MOSFETs M₂₈ and M₃₀ are four times larger than the channel widths of the MOSFETs M₂₉ and M₃₁. The direction of the resulting current is changed using the cascoded current mirror formed by MOSFETs M₃₂, M₃₃, M₃₄, and M₃₅.

Figure 3 

Complete circuit schematic of the proposed controllable constant power generator.

DC current source I₁ (I₂) is realized by using CCII. Its differential input stage is formed by the MOSFETs M₃₇ and M₃₈ (M₅₀ and M₅₁), with the active cascoded load MOSFETs M₃₉, M₄₀, M₄₁, and M₄₂ (M₅₂, M₅₃, M₅₄, and M₅₅). The differential input stage is biased by MOSFET M₃₆ (M₄₉) and biasing voltage V_B3. The current at terminal X of this CCII is V_C1/R₁ (V_C2/R₂), and it is multiplied by the factor of eight by the two output cascoded current mirror MOSFETs M₄₃, M₄₄, M₄₅, M₄₆, M₄₇, and M₄₈ (M₅₆, M₅₇, M₅₈, M₅₉, M₆₀, and M₆₁). So, the output current of this current source is I₁ = 8V_C1/R₁ (I₂ = 8V_C2/R₂). To change the direction of the current I₂, the wide-swing current mirror is used. This current mirror consists of MOSFETs M₆₂, M₆₃, M₆₄, and M₆₅ and biasing voltage V_B4. The current mirror formed by MOSFETs M₆₆, M₆₇, M₆₈, and M₆₉ is used to sum currents I₁ and I₂ and to divide the sum of the currents by four. In that aim, the channel widths of the MOSFETs M₆₆ and M₆₈ are four times larger than the channel widths of the MOSFETs M₆₇ and M₆₉. The direction of the resulting current is changed using cascoded current mirror formed by MOSFETs M₇₀, M₇₁, M₇₂, and M₇₃.

The generated power of the proposed controllable constant power generator is given by

3. Stability Analysis

Controllable constant power generators usually suffer from stability problems [1, 3]. The range of resistive loads and the range of generated power are often reduced as a consequence of this problem [1, 3]. The stability analysis of the proposed controllable constant power generator is performed through the derivation of the loop gain Aβ(s). In the small-signal analysis, the CCII, whose voltage input Y is connected to the active terminal of the resistive load (the output of the multiplier/divider circuit), is modelled as shown in Figure 4 [11, 12]. Capacitance C_X is the input capacitance at terminal X of the CCII, resistance R_X is the input resistance at terminal X of the CCII, capacitance C_Y is the input capacitance at terminal Y of the CCII, capacitance C_Z1 is the output capacitance at terminal Z₁ of the CCII, resistance R_Z1 is the output resistance at terminal Z₁ of the CCII, capacitance C_Z2 is the output capacitance at terminal Z₂ of the CCII, and resistance R_Z2 is the output resistance at terminal Z₂ of the CCII. The terminal X of the CCII is connected to the active terminal of the resistor R_REF. The terminal Y of the CCII is connected to the active terminal of the resistive load R_L. The terminal Z₁ of the CCII is connected to the source of the MOSFET M_2a, and the terminal Z₂ of the CCII is connected to the drain of the MOSFET M₉. Current mirrors within multiplier/divider circuit are modelled as simple ones.

Figure 4 

Small-signal model of the second generation current conveyor [11, 12].

The loop gain Aβ(s) of the proposed controllable constant power generator is given by where the zeroes ω_zi and the poles ω_pi are where , , , , , and are the transconductances of the saturated MOSFETs M_1a, M_2a, M_3a, M_4a, M_28a, and M_34a, respectively, C₁ is the parasitic capacitance at the drain of the MOSFET M_4a, C₂ is the parasitic capacitance at the gate of the MOSFET M_1a, C₃ is the parasitic capacitance at the drain of the MOSFET M_6a, and C₄ is the parasitic capacitance at the drain of the MOSFET M₉. It is calculated that the DC loop gain ranges from |Aβ(s = 0)|≈0.01, for the lower limit of the resistive loads, to |Aβ(s = 0)|≈0.3, for the upper limit of the resistive loads, for appropriate generated powers. The parasitic capacitances C₁, C₂, C₃, and C₄ are in the order of 1 pF, while the parasitic capacitances C_X, C_Y, C_Z1, and C_Z2 are in the order of 100 fF. The transconductances of saturated MOSFETs are calculated as  = (2β_iI_Di)^1/2_.

The absolute value of the loop gain frequency characteristic |Aβ(jω)|, for the lower limit of the resistive loads and for the appropriate generated powers, is shown in Figure 5. The frequency of the first zero ω_z1 is about 150 MHz, the frequency of the next pole ω_p2 is about 200 MHz, the frequency of the next pole ω_p1 is between 300 MHz and 400 MHz, the frequency of the next pole ω_p3 is in the order of 10 GHz, and the frequency of the last zero ω_z2 is in the order of 100 GHz. The absolute value of the loop gain frequency characteristic |Aβ(jω)|, for the upper limit of the resistive loads and for the appropriate generated powers, is shown in Figure 6. The frequency of the first pole ω_p1 is between 30 MHz and 130 MHz, the frequency of the next zero ω_z1 is about 150 MHz, the frequency of the next pole ω_p2 is about 250 MHz, the frequency of the next pole ω_p3 is in the order of 10 GHz, and the frequency of the last zero ω_z2 is in the order of 100 GHz. As the absolute value of the loop gain frequency characteristic |Aβ(jω)| never reaches the value of 0 dB, the system is stable.

Figure 5 

The absolute value of the loop gain frequency characteristic of the proposed controllable constant power generator, for the lower limit of the resistive loads and for the appropriate generated powers.

Figure 6 

The absolute value of the loop gain frequency characteristic of the proposed controllable constant power generator, for the upper limit of the resistive loads and for the appropriate generated powers.

4. Simulated Results

The circuit is designed and simulated using PSpice with BSIM3 version 3.1 transistor model for TSMC 0.35 μm n-well CMOS process obtained by MOSIS. The circuit is single supplied by V_DD = 5 V. Biasing voltages have the following values: V_B1 = 3 V, V_B2 = 3.1 V, V_B3 = 0.8 V, and V_B4 = 1.9 V. Resistances have the following values: R₁ = 8 kΩ, R₂ = 8 kΩ, and R_REF = 1.25 kΩ.

The current I_L flowing through the resistive load as a function of the voltage V_L across the resistive load, for the generated power P_L = 5 mW, is shown in Figure 7. The resistance R_L is changed from 400 Ω to 2.2 kΩ. Larger values of the voltage across the resistive load (corresponding to larger resistive load) are out of the input voltage range of the CCII, whose input is connected to the active terminal of the resistive load, for a given supply voltage. For larger values of the current flowing through the resistive load (corresponding to smaller resistive load), the multiplier/divider circuit shows larger errors caused by the channel length modulation of the MOSFET M_1a. The current I_L flowing through the resistive load increases rapidly with the decrease of the resistive load R_L due to square-hyperbolic dependence between them, I_L=√P_L/√R_L. The source-to-gate voltage V_SG7a of the MOSFET M_7a also increases rapidly, and the drain-to-source voltage V_DS1a of the MOSFET M_1a decreases rapidly.

Figure 7 

Current I_L flowing through the resistive load versus voltage V_L across the resistive load of the proposed controllable constant power generator, for generated power P_L = 5 mW. The current −I(R_L) is, in fact, the current I_L. The voltage V₂(R_L) is the voltage V_L.

Generated power P_L of 5 mW of the proposed controllable constant power generator for variable load resistances 500 Ω < R_L< 1.5 kΩ is shown in Figure 8. Relative error of generated power is −0.6% < E_L< 0.1%. The generated power is calculated (6), and the system is calibrated for the load resistance of 1 kΩ.

Figure 8 

Generated power P_L versus load resistance R_L of the proposed controllable constant power generator, for control voltages V_C1 = 1.5 V and V_C2 = 2.67 V. The current −I(R_L) is, in fact, the current I_L. The voltage V₂(R_L) is the voltage V_L.

Generated powers P_L = {0.5 mW, 1 mW} of the proposed controllable constant power generator for variable load resistances 1 kΩ < R_L< 15 kΩ are shown in Figure 9. Generated powers P_L = {2 mW, 3 mW, 4 mW, 5 mW, 6 mW, 7 mW, 8 mW, 9 mW} of the proposed controllable constant power generator for variable load resistances 400 Ω < R_L< 5.5 kΩ are shown in Figure 10. Table 1 shows summarized results of the proposed controllable constant power generator. The range of resistive load R_L, for different values of dissipated power P_L, as well as the values of corresponding control voltages V_C1 and V_C2 is shown. The main demand was that the relative error of generated power is |E_L| < 2%. For smaller generated power 0.5 mW ≤ P_L ≤ 4 mW, the load resistance dynamic range is larger. It ranges from 15 (1 kΩ ≤ R_L ≤ 15 kΩ, for P_L = 0.5 mW) to 7 (0.4 kΩ ≤ R_L ≤ 2.8 kΩ, for P_L = 4 mW). For larger generated power 5 mW ≤ P_L ≤ 9 mW, the load resistance dynamic range is smaller. It ranges from 5.5 (0.4 kΩ ≤ R_L ≤ 2.2 kΩ, for P_L = 5 mW) to 2.4 (0.5 kΩ ≤ R_L ≤ 1.2 kΩ, for P_L = 9 mW).

Figure 9 

Generated powers P_L = {0.5 mW, 1 mW} versus load resistance R_L of the proposed controllable constant power generator. The current −I(R_L) is, in fact, the current I_L. The voltage V₂(R_L) is the voltage V_L.

Figure 10 

Generated powers P_L = {2 mW, 3 mW, 4 mW, 5 mW, 6 mW, 7 mW, 8 mW, 9 mW} versus load resistance R_L of the proposed controllable constant power generator. The current −I(R_L) is, in fact, the current I_L. The voltage V₂(R_L) is the voltage V_L.

Table 1 

Values of generated power P_L, resistive load R_L, control voltages V_C1 and V_C2, for relative error of generated power |E_R| < 2%.

For smaller generated powers, the minimal value of the load resistance is limited by the input voltage offset of the CCII whose input is connected to the active terminal of the resistive load. That offset voltage is not constant over the all input voltage range of the current conveyor. Small absolute change of the offset voltage produces large enough relative change of the current I₃ that leads to the larger relative error of the generated power.

The main limitation for load resistance dynamic range, for all generated powers, is the supply voltage that directly affects the input voltage range of the CCII whose input is connected to the active terminal of the resistive load and the output current range of the multiplier/divider circuit. With larger supply voltage, it also would be possible to generate larger powers, as well as the larger range of generated powers.

In order to prove that the proposed controllable constant power generator is not particularly influenced by the process parameter variations, Monte Carlo simulations have been performed. The following process parameters have been changed within Monte Carlo simulations: carrier mobility, threshold voltage (for the source-to-bulk voltage V_SB = 0), body effect coefficient, and channel length modulation coefficient of all MOSFETs, as well as the resistances R₁, R₂, and R_REF. These values have been changed for 10% related to the nominal values for 100 runs. The nominal value of the generated power of P_L = 5 mW is changed with process parameter variations from 4.5 mW to 5.6 mW for the load resistance 500 Ω < R_L< 1.5 kΩ. By analyzing the individual influence of a certain process parameter variations, it can be shown that the change of the generated power is dominantly caused by the variations of the resistances R₁, R₂, and R_REF. Although there is a change in the value of the generated power, it is important to stress that the relative error of the generated power is not affected by the process parameter variations. The absolute values of these relative errors range from 0.02% to 2.65% only. These relative errors are calculated related to the power generated for the load resistance R_L = 1 kΩ for each corresponding run. Distribution of these relative errors in the form of a histogram is shown in Figure 11. The absolute value of the relative error is less than 0.5% in 28% runs, less than 1% in 73% runs, and less than 1.5% in 95% runs.

Figure 11 

Distribution of the absolute value of the relative error E_R.

In order to investigate the temperature influence to the proposed design, the generated power P_L = 5 mW of the controllable constant power generator for variable load resistance 0.5 kΩ < R_L< 1.5 kΩ with the temperature used as a parameter T∈{−20°C, −10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, 60°C, 70°C, 80°C} has been simulated. Two types of the simulations have been performed. In the first one shown in Figure 12, the resistances R₁, R₂, and R_REF are constant, that is, temperature independent. In the second type shown in Figure 13, the temperature influence to the resistances R₁, R₂, and R_REF is modeled by using the linear temperature coefficient α= − 3×10⁻³/K. This is the typical value of the linear temperature coefficient of the resistor made by using a high resistivity poly in a standard 0.35 μm CMOS technology. The relative error is calculated related to the power generated for the load resistance R_L = 1 kΩ at T = 27°C. For the temperature-independent resistance R₁, R₂, and R_REF (Figure 12), the absolute value of the relative error is up to 8%. On the other hand, for the temperature-dependent resistances R₁, R₂, and R_REF (Figure 13), the absolute value of the relative error ranges is up to 12%. It is clear that the proposed controllable constant power generator is dominantly influenced by the temperature variations of the resistances R₁, R₂, and R_REF compared to the influence of the temperature variations of the active components_. In order to reduce the temperature influence to the proposed design, according to the relation (6), either the resistors R_REF and R₁, or R_REF and R₂ have to be of the same type, while either the resistor R₂ or the resistor R₁ has to be designed with predetermined temperature coefficient (e.g., zero temperature coefficient). To that aim, either the resistor R₂ or the resistor R₁ can be designed as a composite one [13–15] with predetermined (zero) temperature coefficient. With this composite resistor, it can be expected that the overall temperature influence to the proposed controllable constant power generator will be similar to that shown in Figure 12 or even smaller. For the specific application of the proposed design in the plant tissue humidity measurements in the open arable field, the temperature range of interest is from 0°C to 50°C. In that case, the absolute value of the relative error is up to 3.5% for the temperature-independent resistances R₁, R₂, and R_REF and up to 8% for the temperature-dependent resistances R₁, R₂, and R_REF.

Figure 12 

The generated power P_L = 5 mW of the proposed controllable constant power generator versus load resistance for temperatures T∈{−20°C, −10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, 60°C, 70°C, 80°C}, with temperature-independent resistors. The current −I(R_L) is, in fact, the current I_L. The voltage V₂(R_L) is the voltage V_L.

Figure 13 

The generated power P_L = 5 mW of the proposed controllable constant power generator versus load resistance for temperatures T∈{−20°C, −10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, 60°C, 70°C, 80°C}, with temperature-dependent resistors. The current −I(R_L) is, in fact, the current I_L. The voltage V₂(R_L) is the voltage V_L.

Simulations of the frequency response of the CCII M₁₁-M₂₃ (Figure 3) are shown in Figures 14 and 15. The DC biasing voltage at the terminal Y of the CCII is used as a parameter and is changed from 0.7 V to 3.28 V with a step of 0.43 V. This DC biasing voltage corresponds to the DC voltage V_L across the resistive load R_L for the generated powers 0.5 mW < P_L< 9 mW and corresponding load resistance range. The load at the terminal Z is presented by the wide-swing current mirror M₂₄-M₂₇, with the drain of the MOSFET M₂₇ connected to the supply voltage source V_DD. The CCII has been optimized to achieve the gain-peaking less than 3 dB in the frequency responses for all ranges of the DC biasing voltage at the terminal Y of the CCII. The frequency voltage transfer characteristic v_x/v_y is shown in Figure 14. The bandwidth ranges from 39 MHz (V_Y = 0.7 V, P_L = 0.5 mW) to 125 MHz (V_Y = 3.28 V, P_L = 9 mW). The frequency transconductance transfer characteristic i_z/v_y is shown in Figure 15. The bandwidth ranges from 39 MHz (V_Y = 0.7 V, P_L = 0.5 mW) to 137 MHz (V_Y = 3.28 V, P_L = 9 mW).

Figure 14 

The frequency voltage transfer characteristic v_x/v_y. The voltage V(R_REF:2) is, in fact, the voltage v_x.

Figure 15 

The frequency transconductance transfer characteristic i_z/v_y. The current ID(M₂₆) is, in fact, the current i_z.

In order to prove that the proposed controllable constant power generator is stable, simulations of the transient response to a step change of the load resistance R_L have been performed. The voltage-controlled resistor [12, 16] is used as the resistive load R_L in order to simulate the step change of the resistance, Figure 16. The voltage follower within the voltage-controlled resistor is designed similar to that in [12], but with MOSFETs only. The resistors within the resistive voltage divider have the same resistances, R₃ = R₄. The load resistance is a step changed from R_L = 0.707 kΩ to R_L = 1.299 kΩ, as the control voltage is a step changed from V_C = 2.5 V to V_C = 1.6 V. The rise time and the fall time of the load resistance are 28 ns and 19 ns, respectively. The voltage V_L across the voltage-controlled resistor (resistive load R_L) is shown in Figure 17. The product of the voltage V_L and the current I_L of the voltage-controlled resistor is constant and equal to P_L = V_LI_L = 5 mW. It can be seen that there is no overshoot in the transient responses which confirms the unconditional stability of the proposed design predicted by the mathematical model expressed by (7), (8), (9), (10), (11), and (12) and Figures 5 and 6. In addition, it can be estimated that the largest frequency bandwidth in the considered example is up to 5 MHz.

Figure 16 

The circuit used for simulations of the transient response to a step change of the load resistance R_L using voltage-controlled resistor.

Figure 17 

The output voltage of the controllable constant power generator for step change of the resistive load from R_L = 0.707 kΩ to R_L = 1.299 kΩ. The voltage V(M_1vcr:d) is, in fact, the output voltage of the controllable constant power generator in this analysis.

5. Discussion and Conclusions

Proposed controllable constant power generator based on multiplier/divider circuit is designed and simulated in 0.35 μm CMOS technology. It is possible to generate small power from 0.5 mW to 1 mW for load resistance from 2.5 kΩ to 10 kΩ (variation from −50% to 100%, for the load resistance R_L = 5 kΩ), with the relative error of generated power less than 1.2%. These results are shown in Table 2. Also, it is possible to generate larger power from 1 mW to 7.8 mW for load resistance from 0.5 kΩ to 1.5 kΩ (variation of ±50%, for the load resistance R_L = 1 kΩ), with the relative error of generated power less than 2%. These results are shown in Table 3. The circuit is optimized for 5 V single supply. The ratio of the largest voltage drop across the resistive load and the supply voltage (V_Lmax/V_DD) is 68%, which is a better result than 58% in [1], 40.6% in [3], and 44% in [4–6]. The supply voltage and power dissipation of the circuit are limiting factors in many applications, especially in the open field, powered by the solar cells. For different applications, where power consumption of the circuit is not critical, it would be possible to generate larger power, with wider load resistance dynamic range, with a higher value of the supply voltage.

Table 2 

Values of generated power P_L and corresponding relative error E_R, for resistive load 2.5 kΩ < R_L< 10 kΩ.

Table 3 

Values of generated power P_L and corresponding relative error E_R, for resistive load 500 Ω < R_L< 1.5 kΩ.

Compared to the design presented in [1], proposed controllable constant power generator, for the load resistance range from 500 Ω to 1.5 kΩ, has the smaller range of generated power, with the same level of relative error, but with the 5 V single supply, compared to 7 V single supply. The design presented in [1] has larger load resistance dynamic range, but with 10 V single supply. Compared to the design presented in [3], proposed controllable constant power generator, for the load resistance range from 500 Ω to 1.5 kΩ, has the smaller range of generated power, but the smaller relative error with the 5 V single supply, compared to ±5 V supply voltage. The proposed controllable constant power generator also has larger load resistance dynamic range for the particular generated power, compared to the design presented in [3]. The largest relative error of the proposed design is 6 times smaller than in [10] for the same load resistance range, for the generated power 0.5 mW < P_L< 12 mW. The frequency bandwidth of the proposed controllable constant power generator is approximately 500 times larger than in [1] and more than 6400 times larger than in [9]. The performance comparison between the proposed controllable constant power generator and controllable constant power generators presented in [1, 3], for resistive load 0.5 kΩ < R_L< 1.5 kΩ is given in Table 4. The proposed design has no stability problems for all generated powers over a wide range of the resistive loads. Based on achieved results, it can be concluded that the controllable constant power generator can be used in various thermal-based sensor applications.

Table 4 

Performance comparison between the proposed controllable constant power generator and previous controllable constant power generators.

Conflicts of Interest

The author declares that there is no conflict of interest regarding the publication of this paper.

Acknowledgments

This work has been supported by the Ministry of Science of Montenegro and the HERIC project through the BIO-ICT Centre of Excellence (Contract no. 01-1001).