Research Article
ARM-Based Universal 1-Wire Module Solution
Table 4
Parameters of 1-wire communication timing.
| | Parameter | Description | Time (μs) |
| | W_ONE | Master write log. 1—drive bus low. | 6 | | OW_BOOSTER | After releasing bus, master activate force “1.” | 10 | | W_ONE_DELAY | After this time, master release bus. | 54 | | W_ZERO | Master write log. 0—drive bus low. | 60 | | R_PULSE | Master send read pulse—drive bus low, then release bus. | 6 | | R_PRESENCE | Time when master sample level of 1-wire bus. | 9 | | R_DELAY | Time to activate force “1” by the master. | 45 |
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