A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit
This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs) to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.
The Hall plate is a type of a CMOS magnetic induction sensor that can sense the magnetic induction perpendicular to the sensor plate surface and convert it into a corresponding electrical signal such as voltage, current, or frequency [1–3]. That is, the CMOS Hall sensor can be used in output of either voltage (voltage mode) or current (current mode). In both modes, sensitivity and offset are valuable features for evaluating the performance of the Hall sensor . Various techniques have been developed to improve these characteristics based on conventional voltage-mode Hall sensors [5–8]. Voltage-mode Hall sensors have dominated most applications for many years [2, 4]. A cross-shaped Hall plate (CSHP) is a widely used Hall sensor that uses a Wheatstone bridge topology . However, the Hall plate achieves lower voltage-related magnetosensitivity than the magnetotransistor or the MAGFET  does. To enhance magnetosensitivity, the hybrid magnetosensor has been developed to have a large output Hall current, which is the drain current of MOSFET whose gate is biased with a polysilicon CSHP in voltage mode. Notably, the magnetosensitivity is enhanced because the drain current of MOSFET is a quadratic equation of the induced Hall voltage at a gate terminal and because the offset is effectively eliminated with an instrumentation amplifier (IA).
The split-drain MAGFET is used as a Hall sensor by sensing the magnetic induction perpendicular to the MAGFET plane, in which a current difference is obtained between two adjacent drains of the MAGFET . The relative sensitivity depends on the primary geometric parameters and biasing conditions of the applied device [11, 12]. Among all the proposed shapes in , measurements show that the sectorial structure with two 90° lobes exhibits the most sensitivity with respect to the magnetic induction. That is, a symmetrical and differential structure enables favorable sensitivity. In addition to the geometric parameters, the biasing condition should be considered. As shown in , the strip approach can carry the biasing current up to 500 mA, whereas the biasing current in the coil approach is limited to 20 mA. The biasing current of the strip MAGFET with two sources is superior to that of the MAGFET with a shared source . Additionally, an obvious advantage to the operation of CMOS systems is that thermal noise is reduced , whereas the flicker noise remains fairly temperature independent . This paper proposes a hybrid magnetosensor composed of a polysilicon CSHP and a pair of identical MOSFETs. The MOSFET enhances the magnetic sensitivity with a quadratic equation of the induced Hall voltage at the polysilicon CSHP, and the strip structure with two separated sources improves the biasing current.
Additionally, this paper proposes a SPICE macro model that is suitable for detecting the magnetic induction in voltage mode [16, 17]. Both simulated and measured results are provided to verify the correctness and flexibility of the proposed SPICE macro model. The rest of this paper is organized as follows: Section 2 describes the operational principles of the proposed topology of the 1-D hybrid magnetosensor and its SPICE macro model. Section 3 presents the readout circuit for the magnetosensor. Section 4 provides simulated and measured results of the magnetic chip. Section 5 presents the discussion and the conclusions.
2. Operational Principle of the Hybrid Magnetosensor
Figure 1 presents the proposed 1-D hybrid magnetosensor, which is composed of a polysilicon CSHP as shown in Figure 1(a) and a pair of identical MOSFETs, M1 and M2, as shown in Figure 1(b), to sense the magnetic induction BZ perpendicular to the chip surface. Here, Ibias is the biasing current in the y-direction and FX is the Lorentz force in the x-direction. The polysilicon CSHP is located on M1 and M2 to establish a hybrid magnetosensor, which is a magnetically coupled current sensor using CMOS split-drain transistors with a high biasing current . In the absence of the applied magnetic induction BZ, two output currents, ID1 and ID2, are the same at D1 and D2 of MOSFETs M1 and M2, respectively. After passing through the readout circuit, the output voltage VOUT of the IA is constant. That is, ΔVOUT = 0. In contrast to BZ = 0, the output voltage VOUT is a function of the bias current Ibias with respect to the applied magnetic induction BZ.
As shown in Figure 1(a), a magnetic induction BZ and a bias current Ibias are applied to the polysilicon CSHP and the positive and negative Hall voltages, VH(+) and VH(−), are induced by a Lorentz force FX in the x-direction. After putting the polysilicon CSHP on the two identical MOSFETs as shown in Figure 1(c), two drain currents, ID1 and ID2, can be expressed by grounding two sources, S1 and S2. That is, where μn, Cox, W, L, and VTH are the electron mobility, parasitic capacitance per unit gate area, width, length, and threshold voltage, respectively. VGS is the gate-to-source voltage without magnetic induction. The induced Hall voltage VH is then derived from the Lorentz force. where represents the Hall coefficient, Ibias is the bias current in the y-direction, BZ is the magnetic induction in the z-direction, and t and G are the polysilicon thickness and the geometrical correction factor, respectively . Thus, the current difference between ID1 and ID2 can be expressed as
Rewriting (3), we have
Consequently, the current difference ΔID is directly proportional to the bias current Ibias and the magnetic induction BZ. When the bias current is set to be constant, the larger the magnetic induction BZ is, the higher the induced current difference ΔID is. A comprehensive macroanalysis is presented in Figure 2 to facilitate comprehension of the Hall effect at the proposed 1-D hybrid magnetosensor fabricated using standard 0.18 μm CMOS technology. The physical mechanism is proposed to involve the Lorentz force FX pushing the positive charge right to gather it at the right side of the polysilicon CSHP, which is connected to the gate terminal of the second MOSFET M2. Thus, the drain current of the M2 is a quadratic equation of the induced positive Hall voltage VH(+) at the gate terminal. The magnetic sensitivity could be improved effectively. Meanwhile, the electron current is directly injected into the left side of the polysilicon CSHP, which is connected to the gate terminal of the first MOSFET M1 to reduce the drain current of the M1. The corresponding netlist file is provided in the appendix. By applying a magnetic induction BZ (~mT), the output voltage VOUT at the output of the readout circuit can be measured by multiplying the induced differential drain voltage, VO1 − VO2, by 43 dB. Note that the differential drain voltage is equal to the current difference ΔID multiplied by the external resistor RD (~50 Ω). In the netlist file, the voltage source V(mag_in) represents the induced Hall voltage, which is generated with the applied magnetic induction BZ. Figure 3 shows those equivalent resistors of the proposed polysilicon CSHP. Two resistors, Rin2 and Rout1, are reduced by the Lorentz force FX which pushes those carriers to the right of the CSHP; meanwhile, Rin1 and Rout2 are increased with the Lorentz force.
3. Readout Circuit
Two drain currents, ID1 and ID2, obtained at two separate drains of the MAGFET sensor over the considered magnetic induction range are of the order of a few tens of microamperes. By passing the current signal through the current-to-voltage converter (I-to-V converter) and low-pass (LP) RC filter, the high-frequency noise is filtered out before the instrumentation amplifier. Figure 4 shows the readout circuit of the proposed hybrid magnetosensor, which includes the I-to-V converter, LP filter, and instrumentation amplifier. The offset can be removed by the instrumentation amplifier, and a single output VOUT is easy to use.
As shown in Figure 4, the I-to-V converter is employed to convert the induced drain current obtained from the proposed 1-D magnetosensor. Two output voltages of the I-to-V converter can be expressed as where VO1 and VO2 are the output voltages of OP1 and OP2, respectively. VREF1 and VREF2 represent the two reference voltages for adjusting the bias voltages in operational amplifiers OP1 and OP2. RD is the drain resistor which is equal to RD1 and RD2 in Figures 2 and 4. The output voltage of the instrumentation amplifier VOUT passing through the LP filter is given by where VREF3 is a constant reference voltage, which is used to adjust the output level. For DC magnetic induction, s = 0; the small-signal output voltage is given by
Next, we address the offset voltage, which is contributed by three reference voltages, for the DC magnetic induction. That is,
Note that the voltage difference, ΔVREF = VREF1 − VREF2, plays a dominant role in the offset voltage because it is amplified by . A large offset voltage limits the output range considerably. Furthermore, the drain resistor RD is completed with the common-centroid layout to eliminate the impact of noise, and the resistors, R2, RA, RB, RC, and RG, and capacitor C1 are the external components.
Figure 5 shows the folded cascode operational amplifier (op amp) with a cascode PMOS load that performs with a large differential output voltage swing, and the choice of the input common-mode level is easy . The left part of Figure 5 depicts a bias circuit that is used to provide three constant bias voltages, V1, V2, and V3. To obtain a single-ended output, the active PMOS load (M17–M20) can be modified (Figure 5) so that M17 and M18 are biased at the edge of the triode region. The adopted folded cascade amplifier saves one PMOS threshold voltage in the output swing .
As shown in Figure 5, we employ “two-stage” op amps, with the first stage providing a high gain and the second stage typically configured as a simple common-source stage to allow maximum output swings . The first and second stages exhibit gains equal to Av1 and Av2, respectively, and the swing at VOUT is equal to VDD − |VOD25| − VOD26. The overall voltage gain Av can be expressed as where , , and rOi are the transconductance, body transconductance, and output resistance, respectively, of the ith MOSFET.
The right half plane zero is a serious concern in two-stage CMOS op amps because is relatively small and the compensation capacitor CC is set to be sufficiently large to position the dominant pole properly. As shown in Figure 5, the zero frequency ωz can be modified by placing a resistor Rz in series with the compensation capacitor. The zero frequency is then given by 
Thus, if , then ωz ≤ 0. In practice, we can move the zero well into the left half plane to cancel the first nondominant pole. This occurs if
That is, where CE denotes the capacitance at node E before CC is added .
4. Simulated and Measured Results
In general, voltage-mode Hall devices can be biased in two modes: voltage biasing and current biasing . In the current biasing mode, the current-related sensitivity SRI is calculated as where the unit of SRI is V·A−1·T−1, Ibias represents the supply bias current, ΔB is the change in the applied magnetic induction, and ΔVOUT is an output voltage difference of the instrumentation amplifier with and without magnetic induction B. In the voltage biasing mode, the voltage-related sensitivity SRV is defined as where the unit of SRV is the inverse tesla (T−1) and Vbias is the supply bias voltage . In addition, the nonlinearity error (NLE) is defined as where the NLE is expressed as a percentage and ΔV(0)OUT is the calculated output voltage based on the slope of the straight line obtained according to the best fit to the output characteristic .
This study presents a high-gain, high common-mode rejection ratio (CMRR), and low-noise folded cascode op amp fabricated using 0.18 μm CMOS technology for magnetic measurements. By employing the folded cascode architecture and common-mode feedback at the output, a substantial improvement was achieved in the gain and the CMRR . Furthermore, a low-noise amplifier was achieved by using a differential pair and minifying the transistor size . The designed folded op amp has a gain of 105 dB, phase margin of 80°, CMRR of 110 dB, slew rate of 2.0 V/μs, input common-mode range (ICMR) of 2.0 V, gain bandwidth of 1 kΩ, averaged power supply rejection ratio (PSRR) of 118 dB, output swing of 1.8 V, input-referred noise of 10.8 at 1 MHz, power consumption of 0.88 mW at a power supply of 1.8 V, and load capacitance of 10 pF in the TT design corner. Figure 6 shows the simulated AC analysis of the op amp circuit along with the phase response in five design corners exhibiting a DC voltage gain of 105 dB and a phase margin of 80° in the TT corner. The variations of simulated voltage gain and phase margin are small. Figure 7 shows the simulated input-referred noises at five design corners with respect to frequency. Table 1 summarizes the simulated input-referred noises at five design corners with respect to two frequencies: 400 kHz and 1 MHz. The op amp exhibits low noise in the FF design corner but high noise in the SS design corner. Note that the optimum representative frequency is about 1 MHz due to the gain bandwidth of 1 kHz in Table 2.
The simulated and measured results are tabulated in Table 2, and a comparison with previous studies was conducted. The simulated results such as the voltage gain, CMRR, slew rate, ICMR, gain bandwidth, PSRR, output swing, and input-referred noise are superior to those of [21–23]. The measured data verify that the designed op amp operates correctly even though the aforementioned studies have yet to prove so. Figure 8 shows the microphotograph of the proposed magnetic chip without external resistors and capacitors, which was fabricated in a 0.18 μm CMOS process. A voltage gain of 43 dB is always required for the instrumentation amplifier, whose OPs are completed with the same folded cascade topology. Figure 9 shows the magnetic induction generator that is used to generate 1-D magnetic induction BZ.
As presented in , the measured Hall current is evident when the bias current Ibias is greater than 100 μA for the four-folded vertical Hall device. Thus, the bias current was set to 100, 200, and 300 μA in both simulation and measurement. According to the proposed SPICE model shown in the appendix, the simulated output Hall voltages are presented (Figure 10; dashed lines) as a function of the different biasing currents, from 100 μA to 300 μA in steps of 100 μA, at different magnetic inductions, from −30 mT to 30 mT in steps of 5 mT. The measured output Hall voltages are plotted using symbols denoting the three bias conditions. As shown in Figure 10, the measured data closely match the simulation data. Both the simulated and measured results were obtained with the readout circuit for the proposed magnetic chip.
After the proposed SPICE model was verified with the measurements, low magnetic induction was considered to find the minimum resolution with good linearity [25, 26]. Figure 11 shows the simulated output voltages (dashed lines) and measured output voltages (mark symbols) as a function of applied magnetic induction, from −30 G to 30 G in steps of 6 G, where 1 T is equal to 104 G. The bias currents were selected as 100 μA, 200 μA, and 300 μA. The nonlinearity between the output Hall voltage and applied magnetic induction is poor when the bias current is low, especially for Ibias = 100 μA. Comparing Figure 12 with Figure 13, we find that the NLE of Figure 13 is larger than that of Figure 12. That is, the variation of NLE is large when the magnetic chip operates at low magnetic induction and low bias current.
Table 3 summarizes all the measured results of the proposed magnetic chip including the readout circuit. The NLE is inversely proportional to the bias current Ibias, but the measured Hall voltage VH is proportional to the bias current. The maximum magnetosensitivity of 520.5 V/A·T or 40.04 V/V·T is obtained at the output Hall voltage of 3.123 mV, the bias current of 200 μA, and the applied magnetic induction of 30 mT. The averaged NLE is small at high magnetic induction of ±30 mT, whereas it is large at low magnetic induction of ±30 G (±3 mT). The measured results show that the proposed 1-D magnetic chip performs with good magnetosensitivity, but it exhibits poor linearity at low bias current and low magnetic induction. Table 4 summarizes all the calculated results of the proposed magnetic chip without a readout circuit. Table 5 presents a comparison between this work and the previous vertical Hall sensors. The optimum current-related magnetosensitivity SRI is 3.6855 V/A·T, which is superior to that in . In addition, the optimum voltage-related magnetosensitivity SRV is 0.2835 V/V·T, which is superior to that in [28, 29]. The magnetic range is large compared with that in [26, 30], and the bias current is low compared with that in [26–29]. Even though there is no measurement with respect to temperature, we predict that the temperature variation is small for MAGFET fabricated in 0.18 μm CMOS technology .
A SPICE macro model is presented to facilitate comprehension of the Hall effect in the proposed 1-D hybrid magnetosensor, including a polysilicon CSHP and two identical MOSFETs, which was fabricated using standard 0.18 μm CMOS technology. The physical mechanism involves the Lorentz force pushing the positive charge right to gather it at the right side of the polysilicon CSHP, which is connected to the gate terminal of the second MOSFET. Because the equation is quadratic, the drain current ID is amplified quadratically based on the induced Hall voltage. When the drain current signal passes through the readout circuit, the magnetosensitivity is improved effectively by amplifying the induced Hall voltage VH in the polysilicon CSHP. By using the SPICE macro model of the proposed 1-D hybrid magnetosensor, a new Hall magnetic sensor was designed by simulating it in advance. Experimental results closely match the simulation results. The NLE is large when it operates at low magnetic induction and low bias current, even though it is a high-quality magnetic sensor. Compared with previous studies, the optimum current-related magnetosensitivity SRI of 3.6855 V/A·T is superior to that in . Additionally, the optimum voltage-related magnetosensitivity SRV of 0.2835 V/V·T is superior to that in [28, 29]. The measured results illustrate that the proposed 1-D magnetic chip performs with good magnetosensitivity, even though it exhibits poor linearity at low bias current and low magnetic induction. Lowering the magnetic range to ±3 mT expands the practical applications for the proposed magnetic chip.
------------------------1-D Hybrid Magnetosensor---------------------------- -------------------------------SPICE Model-------------------------------------- .subckt ONE_poly Vo1 Vo2 VSource IIN IOUT mag_in sensitive='' MM1 Vo1 G1 VSource VSource nch MM2 Vo2 G2 VSource VSource nch Rin1 VIN G1 '(mag_in)sensitive' Rin2 VIN G2 '(mag_in)sensitive' Rout1 VOUT G1 '(mag_in)sensitive' Rout2 VOUT G2 '(mag_in)sensitive' RD1 VDD Vo1 50 RD2 VDD Vo2 50 VVSource VSource 0 0 .ends
Conflicts of Interest
The authors declare that there are no conflicts of interest regarding the publication of this paper.
The authors would like to thank the Ministry of Science and Technology, R.O.C., for financially supporting this research under Contract MOST 103-2622-E-027-014-CC3. They are grateful to the Chip Implementation Center (CIC), Taiwan, for fabricating the test chip. Samuel Johns is appreciated for his editorial assistance.
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