An Efficient VLSI Linear Array for DCT/IDCT Using Subband Decomposition Algorithm

Table 1

Comparisons between the proposed architecture and the conventional architectures.

8-point DCT/IDCT	The conventional architectures		The conventional pipelined architectures	The proposed high- efficient architecture
	The single-processor architectures [9–11]	The parallel architectures with single memory-bank [15–19]	The pipelined architectures with single memory-bank [1, 9–14]	This work(Sung, Shieh and Hsin, 2010)
Processors	1	8	5 (CORDIC)	—
Real multipliers	2	16	0	4
Real adders	3	18	18	26
RAM (Registers)	64	64	64	16
ROM	6	6	6	10
Hardware complexity	$O(1)$	$O(N-\text{lo}{\text{g}}_{2}N+1)$	$O(N-\text{lo}{\text{g}}_{2}N)$	$O(N/2)$
Computation complexity	$O(N^2)$	$O(2N)$	$O(N)$	$O(5N/8)$
Latency	64	16	8	5
Pipelinability	no	no	yes	yes
Scalability	poor	poor	good	better
Power consumption	poor	poor	good	better