Constructing Dynamic Multiple-Input Multiple-Output Logic Gates

Abstract

Investigation of computing devices with dynamic architecture which makes devices have reconfigurable ability is an interesting research direction for designing the next generation of computer chip. In this paper, we present a window threshold method to construct such dynamic logic architecture. Here, dynamic multiple-input multiple-output (MIMO) logic gates are proposed, analyzed, and implemented. By using a curve-intersections-based graphic method, we illustrate the relationships among the threshold, the control parameter, and the functions of logic gates. A noise analysis on all the parameters is also given. The chips based on the proposed schemes can be transformed into different arrangements of logic gates within a single clock cycle. With these schemes in hand, it is conceivable to build more flexible, robust, cost effective, yet general-purpose computing devices.

1. Introduction

In today's processor designs, transistors are locked down for specific functions. Can we overcome the limitation of fixed structures of static architecture in the next generation of computer? This is an important issue to the practical applications. A reconfigurable technique with dynamic architecture has made it possible to break through the fixed limitations of the current computer systems [1, 2]. In dynamic architecture, systems can flexibly change their hardware configurations during the course of computation according to the demands of various functions.

Using reconfigurable techniques, one can envision future processor architecture to morph into distinct functions, each is suitable for an application at hand [3]. The dynamic architecture currently used in the field programmable gate array (FPGA) technique which constructs dynamic architecture by “rewiring” tiles or computer elements may be termed as dynamic rewiring architecture [4–8]. Recently, another technique based on theories of chaos computing which is different from FPGA was proposed to construct dynamic reconfigurable architecture by harnessing dynamical systems [8–10]. In chaos computing, the programmable gate can be modified by adjusting the system parameters of chaos dynamics [11]. By changing the system parameters, chaotic elements of computing can act as different logic elements and perform various computing tasks [12, 13]. Recently, piecewise-linear systems are also suggested for constructing such dynamic logic architecture [14, 15]. In 2008, a prototype VLSI chip (TSMC CMOS, 0.18?𝜇, 30?Mhz clock) has been designed and developed incorporating proof of concept on chaos computing which establishes the technical feasibility of the chaos-based dynamic logic architecture [16].

In our previous works [14, 15], 2-input 1-output logic gates were considered to construct such dynamical architecture. However, the dynamic MIMO logic gate has received little attention. In this paper, we propose schemes to construct such dynamic MIMO logic gates based on a window threshold mechanism, which can emulate different logic gates, perform different arithmetic tasks, and further have the ability to switch among different operational roles by changing the control instruction. By using a curve-intersections-based method, we analyze the different logic distribution on parameters. Noise plays an important role in designing logic architecture. Here, a detailed noise analysis on all the parameters of dynamic MIMO logic gate is also given. The proposed schemes in this paper are efficient in computation and available in engineering implementations.

2. Schemes for Dynamic MIMO Logic Gates

Our basic scheme is represented by the following M-input N-output logic cell: 𝑦=^𝑀−1_𝑖=0𝐶_𝑖𝐼_𝑖𝐼−𝑘,_out𝑗=0,if−𝛽_𝑗<𝑦<𝛽_𝑗𝐼_out𝑗=1,else, (2.1) where 𝐼_𝑖 is the input signals, 𝐶_𝑖 is the weights of 𝐼_𝑖, 𝐼_out𝑗 is the output signals, 𝛽_𝑗 is the window thresholds (0≤𝑖≤𝑀−1,0≤𝑗≤𝑁−1), and 𝑘 is the control instruction which acts as a controller for dynamic MIMO logic gate.

Now we show how to obtain different logic gates by simply changing the values of parameter 𝑘. We firstly consider an example of 3-input 1-output logic gate whose parameters are selected as 𝐶₀=𝐶₁=𝐶₂=1, 𝛽₀=1.75, and 𝑘=1. If we input (000) for (𝐼₂𝐼₁𝐼₀), then we have 𝑦=−1,|𝑦|=1. Since 1<1.75, the output is 0. Inputting (001/010/100) for (𝐼₂𝐼₁𝐼₀) results in |𝑦|=0. Since 0<1.75, the output is 0. Similarly if we input (011/101/110) or (111) for (𝐼₂𝐼₁𝐼₀), the output is identified to 0 and 1, respectively. Thus, the logic cell performs a 3-input AND gate. It is easy to justify that we can change from AND gate to NOR gate by simply changing parameter 𝑘 from 1 to 2 (for more details, please see Figure 1). Seen from Figure 1, we can know that, if we choose different values of 𝛽₀, the logical performance will change accordingly.

Figure 1 

By changing the parameter 𝑘 from 𝑘1 to 𝑘2, logic function of the cell can transform from logic AND to logic NOR.

In order to analyze different gate distribution of logic cell (2.1), we propose an analysis method, called CIA method (curve-intersection-based analysis method), from which we can obtain the relationships among parameters 𝐼_𝑖, 𝐶_𝑖, 𝐼_out𝑗, 𝛽_𝑗, and 𝑘, and then obtain different regions for different logical functions. There are four steps in the proposed analysis method. First, we determine the domain of 𝑘, calculate, and draw curves of |𝑦| for different inputs (𝐼_𝑀−1⋯𝐼₀), where the x-coordinate is 𝑘 and the y-coordinate is |𝑦|. Second, different values of 𝛽_𝑗 are used to divide the region of |𝑦| into two parts: for the upper part, 𝐼_out𝑗=1 where |𝑦|≥𝛽_𝑗, and, for the lower part, 𝐼_out𝑗=0 where |𝑦|<𝛽_𝑗. In the second step, we can determine different 𝛽_𝑗 regions according to the intersections of curves |𝑦| and boundaries of 𝑘. Third, the positions of intersections for curves of 𝛽_𝑗 and |𝑦| are used to discriminate different regions of parameter 𝑘 which represent different logic functions. Finally, with different values of parameter 𝑘, our proposed logic cell can transform among different logic functions.

Now we use CIA method to analyze the 3-input 1-output logic gate. The relationships among parameters |𝑦|,𝑘, and 𝛽₀ are shown in Figure 2 with the domain −1≤𝑘≤4, where parameter values 𝐶₀=𝐶₁=𝐶₂=1. Figure 2(a) shows the curves of |𝑦| with different combinations of (𝐼₂𝐼₁𝐼₀). Figure 2(b) shows different gate distribution of 𝛽₀. In Figure 2(c), the black points mark intersections of the line 𝛽₀=0.75 with various curves of |𝑦| against 𝑘 for different combinations of (𝐼₂𝐼₁𝐼₀). Thus, different regions of logic functions are produced with different values of 𝑘. Here, the intersection points are termed as the critical points. If parameter 𝑘 is selected at or near these critical points, a small variation of 𝑘 may make the logic function transform from one gate to another. This brings disadvantages for designing robust logic gates against noise. Figure 2(d) shows that logic gates can change its function from one to the other. Seen from Figure 2, we know that the logic cell can change flexibly among different kinds of logic functions by changing parameters 𝑘 and 𝛽₀.

Figure 2 

Different 𝑘 regions for different logics: (a) curves of |𝑦| for different combinations (000),(001/010/100),(110/101/011), and (111), respectively. (b) Different 𝛽0 regions according to the intersections of the curves. In each region, 𝛽0 has similar character. (c) 𝛽=0.75. According to the intersections (black points), we achieve 9 regions of 𝑘. (d) For different 𝑘, the logic cell can perform different logic gates.

In our scheme, 𝐶_𝑖 is important to distinguish different inputs [17]. For 3-input 1-output logic gate, the curves of |𝑦| with different combinations of (𝐶₂𝐶₁𝐶₀) are shown in Figure 3, from which we can see that different combinations of 𝐶_𝑖 can lead to different logic outputs. In order to further illustrate the proposed method, a 3-input 2-output logic gate is considered in Figure 4 which shows different 𝑘 regions for different logic functions. Seen from Figure 2 to Figure 4, we know that the proposed curve-intersection-based analysis method is a general and legible tool to analyze different logic gates.

Figure 3 

Curves of |𝑦| for different combination of (𝐶2𝐶1𝐶0) and (𝐼2𝐼1𝐼0) in (2.1). (a) 𝑦=𝐼2+𝐼1+𝐼0−𝑘,(𝐶2=𝐶1=𝐶0=1). The inputs (001/010/100) can be shown by a curve, and the inputs (101/011/110),(000), and (111) can be shown by other different curves, respectively. (b) 𝑦=2𝐼2+𝐼1+𝐼0−𝑘,(𝐶2=2,𝐶1=𝐶0=1). The inputs (001/010) can be shown by one curve, and the inputs (100/011),(110/101),(000), and (111) can be shown by other different curves, respectively. (c) 𝑦=𝐼2+2𝐼1+𝐼0−𝑘,(𝐶2=𝐶0=1,𝐶1=2). The inputs (001/100) can be shown by one curve, and for the inputs (010/101),(110/011),(000), and (111) can be shown by other different curves, respectively. (d) 𝑦=𝐼2+𝐼1+2𝐼0−𝑘,(𝐶2=𝐶1=1,𝐶0=2). The inputs (100/010) can be shown by one curve, and the inputs (001/110),(101/011),(000), and (111) can be shown by other different curves, respectively. Different logic functions can be obtained from Figures 3(a), 3(b), 3(c) and 3(d) with the same 𝛽0 and 𝑘.

Figure 4 

Different 𝑘 regions for different three-input and two-output logic gates where 𝑦=𝐼2+𝐼1+𝐼0−𝑘, with the rules −𝛽0<𝑦<𝛽0,𝐼out0=0;𝑒𝑙𝑠𝑒𝐼out0=1 and −𝛽1<𝑦<𝛽1,𝐼out1=0;𝑒𝑙𝑠𝑒𝐼out1=1. We can obtain different kinds of multiple-input multiple-output logic gates by changing 𝑘.

For logic gate with 2-input 1-output, a special case of multiple-input multiple-output logic gate, there are 16 possible boolean algebraic functions which are shown in Tables 1 and 2. The details of different logic functions when 𝛽 and 𝑘 belong to different regions are shown in Table 3, where 𝐶₁=1,𝐶₀=0.5, and 𝑦=0.5𝐼₀+𝐼₁−𝑘, if −𝛽<𝑦<𝛽, 𝐼_out=1, else 𝐼_out=0. From Table 3, we can see that the gate can change within logic functions NOR, XOR, AND, 0, 𝑋₅, 𝑋₆, 𝑋₇, and 𝑋₈ by changing values of parameter 𝑘. If we use opposite output of the gate, we have contrary gate which means that the gate can change within OR, XNOR, NAND, 1, 𝑋₂, 𝑋₁, 𝑋₈ and 𝑋₇. Moreover, if we exchange inputs 𝐼₁ and 𝐼₀, we obtain its symmetric gate, that is, the gate can change within NOR, XOR, AND, 0, 𝑋₆, 𝑋₅, 𝑋₃, and 𝑋₄. The above analysis demonstrates that we can use the same cell to produce all the basic logics by adjusting parameter 𝑘 (for more detailed definitions about contrary-gate and symmetric-gate, please see [15]).

Table 1 

Truth table of basic logical NOR, NAND, XOR, OR, AND, 0, and 1.

Table 2 

Truth table of logical XNOR, 𝑋₁, 𝑋₂, 𝑋₃, 𝑋₄, 𝑋₅, 𝑋₆, 𝑋₇, and 𝑋₈.

Table 3 

Logical gates for different values of parameters 𝛽, 𝑘.

Since noise cannot be avoided in designing robust logic cells for implementing gate functions successfully, we must discuss the optimal selections of parameter 𝑘 in presence of noise. Now we begin to discuss a thorough noise analysis on all the parameters 𝑘, 𝛽_𝑗, and the inputs. When 𝑘 is influenced by noise, we have 𝑦=∑^𝑀−1_𝑖=0𝐶_𝑖𝐼_𝑖+𝐷𝜂(𝑡)−𝑘, where 𝜂(𝑡) is an additive zero mean noise and 𝐷 is the noise strength. The additive noise will cause some confusions. Based on CIA method, we know that some confusion domains come into being around curves of |𝑦| in presence of noise. Figure 5 shows confusion domains of 3-input 1-output logic gate where 𝐶₀=𝐶₁=𝐶₂=1 and the band of the domain is 2𝐷. When the combination of (𝑘,𝛽₀) is selected in the grey belts (e.g., the red point), the discrimination of logic gate is confused. In order to avoid the influence of noise, the combination of (𝑘,𝛽₀) should be selected near or at the centers of white belts (e.g., the green point). Since 𝑤=√2/2 (please see Figure 5), we can see that when 𝐷 increases to 𝐷=√2/4, the white belts will disappear, that is to say, to perform a robust gate, 𝐷 should be less than √2/4 in this case. Suppose that the 𝑚th input is influenced by noise, we have 𝑦=∑^𝑚−1_𝑖=0𝐶_𝑖𝐼_𝑖+𝐶_𝑚(𝐼_𝑚+𝐷𝜂(𝑡))+∑^𝑀−1_𝑖=𝑚+1𝐶_𝑖𝐼_𝑖−𝑘=∑^𝑀−1_𝑖=0𝐶_𝑖𝐼_𝑖+𝐶_𝑚𝐷𝜂(𝑡)−𝑘, then the influence of noise on 𝐼_𝑚 is similar to that on 𝑘. In this condition, we can know that the band of confusion domain is 2𝐶_𝑚𝐷 and 𝐷 should be less than √2/(4𝐶_𝑚). Figure 6 shows the confusion domains when 𝛽₀ is influenced, from which we know that 𝑘 should be selected so that intersections of curves 𝑘 and |𝑦| should not fall into the confusion domains.

Figure 5 

Confusing processing domains (grey belts) caused by additive noise. When combination (𝑘,𝛽0) is selected in the grey belts (e.g., the red point), the discrimination of logic gate is confused. In order to avoid the influence of such noise, the combination (𝑘,𝛽0) should be selected at the centers of the white belts (e.g., the green point).

Figure 6 

Confusing processing domains (grey belt) caused by additive noise. When the intersections of curves 𝑘 and |𝑦| fall into the grey belts (e.g., the red point), the discrimination of logic gate is confused. In order to avoid the influence of such noise, the intersections of 𝑘 and |𝑦| should be far away from the grey belt.

Physical implementation of the proposed scheme is an important work for successful engineering applications. Figure 7 shows the simulation circuit of a 3-input 1-output logic gate, where UA741 and OP37CZ are operational amplifiers and ZDX1F and ZPD5.1 are diodes. In the circuit, the operational amplifier of OP37CZ is used to calculate the value of 𝑦, and the other operational amplifiers and diodes are used to determine the output. Figure 8 shows simulation results of inputs, 𝑘, output, and 𝑦, respectively. In practical applications, chips based on our schemes can be designed based on the existing semiconductor technology with no retooling requirement.

Figure 7 

Circuit diagram of 3-input 1-output logic gate where 𝑦=𝐼0+𝐼1+𝐼2−2𝑘 and 𝛽0=8.75.

Figure 8 

Simulation results of time sequences from top to bottom: panel 1, panel 2, and panel 3 show a stream of input signals 𝐼0, 𝐼1, and 𝐼2, determining input set (𝐼0𝐼1𝐼2). Panel 4 shows the control signal of 𝑘 for different logics. Panel 5 shows the output signal 𝐼out. Both these logical functions are consistent with the corresponding 𝑘 values indicated in Panel 4. Panel 6 shows the signals of 𝑦, 𝛽0, and −𝛽0, respectively.

Note that there are two types of multiple-input multiple-output (MIMO) logic gates. The first type with one-control instruction which is given in (2.1). The second type with multicontrol instructions is described as follows: 𝑦_𝑗=^𝑀−1_𝑖=0𝐶_𝑖𝑗𝐼_𝑖−𝑘_𝑗,𝐼_out𝑗=0,if−𝛽_𝑗<𝑦_𝑗<𝛽_𝑗𝐼_out𝑗=1,else. (2.2)

For the M-input N-output logic gate with multicontrol instructions, we can also use the proposed CIA method to analyze the gate distribution. The structure of dynamic MIMO logic gate with multicontrol instructions is more complex than that with only one control instruction. However, the logic functions of dynamic MIMO logic gate with multicontrol instructions are richer than that with only one control instruction.

3. Discussion and Conclusion

Arrays of such morphing logic gates can be conceivably programmed on the run (e.g., by an external program) with satisfactory optimization for tasks at hand. For instance, they may serve flexibly as arithmetic processing units or memory units and can be swapped from one to another as demands.

The computing scheme proposed here is a kind of technique for dynamic logic architecture, and it has an important and practical advantage of flexibility over all the previous computing paradigms of static architecture. Moreover, the architecture of dynamic logic is essentially different from that of FPGA [7, 12]. FPGA contains programmable interconnects that can be rewired to perform different functions [17–19]. The chips based on dynamic logic architecture can be transformed into different arrangements of logic gates in single clock cycles. FPGA is relatively slow to reconfigure, typically taking milliseconds for each rewiring, or about one million times slower than chips of dynamic logic architecture. ChaoLogix, a semiconductor company, has gotten to the stage where it can create any kind of gate from a small circuit of about 30 transistors, and this circuit is then repeated across the chip. The use of a single circuit has huge advantages over FPGA [11]. The way FPGA designed takes up more silicon real estate and consumes more resources than chips of dynamic logic architecture [11]. In schemes of dynamic logic architecture, there is no special difference between a memory element and a processing element. Hence, the duties of damaged cells may be efficiently distributed among other elements [17–20]. The reconfigurable computing systems based on dynamic logic architecture may be more robust than those based on FPGA.

In this paper, we use a threshold mechanism to obtain dynamic MIMO logic cell. Such simple computing units may then support a dynamic computer architecture and serve as ingredients of general-purpose device more flexibly than statically wired hardware as well as dynamic hardware based on dynamical systems. Possible applications of such reconfigurable hardware include digital signal processing, software-defined radio, aerospace and defense systems, ASIC prototyping, cryptography, computer vision, speech recognition, computer hardware emulation, and a growing range of other related areas [21, 22]. Further advantages of reconfigurable hardware include the ability to reprogram in the field, to fix bugs, lower nonrecurring engineering costs, and implement coarse-grained architecture approaches [4].

Acknowledgments

The authors would like to thank the Editor and all the anonymous reviewers for their helpful advices. This paper is supported by the National Natural Science Foundation of China (Grant nos. 61070209 and 61100204), the Specialized Research Fund for the Doctoral Program of Higher Education (Grant no. 200800131028), the Chinese Universities Scientific Fund (Grant no. BUPT2011RC0211), the Fok Ying-Tong Education Foundation for Young Teachers in the Higher Education Institutions of China (Grant no. 121062), the Program for New Century Excellent Talents in University of the Ministry of Education of China (Grant no. NCET-10-0239).