Table 3: Logical gates for different values of parameters , .

Region Gate

0
NOR
0
(I) 0
0
AND
0

0
NOR
(II) XOR
AND
0

NAND
(III) XOR
OR

NAND
(IV) 1
OR

NAND
(V) 1
OR

NAND
(VI) 1
OR