Single-Stage Coupled-Inductor Sepic-Type HB-LED Driver with Soft Switching for Universal Line Input

Abstract

This paper proposes a single-stage Sepic-type high brightness LED driver for universal line input to perform power factor correcting and LED dimming. In the driver, a coupled inductor is introduced to replace with two separate inductors to lower volume and cost. A soft-switching cell is embedded into the driver to obtain zero-voltage switching (ZVS) feature so as to furthermore improve driver efficiency. Mathematical derivation and detailed discussion is presented. A prototype is designed, analyzed and implemented, which demonstrates the feasibility of the driver and verifies the theoretical analysis.

1. Introduction

Power electronic devices with front-end rectifier are widely used in industry, commerce, and transportation, which generate current harmonics, produce power pollution, and result in low power factor. Therefore, there are international harmonic standards (such as IEC-1000 and IEC-555) to confine power pollution. In order to meet the requirements of the standards, the input current waveform of a device has to be shaped by a power factor corrector (PFC) to eliminate current harmonics and improve power factor.

The PFCs can be briefly classified into two types. One is passive and the other is active. Passive-type PFC is mainly constructed by inductors and capacitors. Low efficiency, heavy weight, and large volume are its major disadvantages. Besides, in general power factor merely is improved to around 0.8. For active type, active switch, diode and energy-stored component are used to achieve near unity power factor, of which topologies have Buck, Boost, Buck-Boost, ′Cuk, Zeta, Sepic, and Flyback. Conventional Buck-type PFC can obtain an output voltage smaller than ac input voltage. However, only a power factor of 0.95 is met [1]. The Boost structure attains better power factor correction feature but its output voltage is higher than ac-side voltage, and power components withstand high voltage stresses [2, 3]. The Buck-Boost PFC can obtain an output voltage magnitude either larger or smaller than the input. Nevertheless, there is a polarity reversal on the output, and an isolation driver for active switch is required [4, 5]. The ′Cuk, Zeta, Sepic, and Flyback topologies can resolve the problems caused from the Buck-Boost. Among them the Sepic type possesses better performance in total harmonics distortion (THD), efficiency, and power factor correction [6–13]. However, the Sepic PFC needs two separate inductors like ′Cuk and Zeta.

In this paper a dsPIC-based coupled-inductor Sepic-type converter for high-brightness light-emitting-diode  (HB LED) lighting applications is presented, which can not only step down input voltage directly but also perform power factor correcting, drive LED panel, and complete dimming function. A soft-switching cell is proposed to reduce switching losses, improving efficiency. In addition, a bypass circuit in parallel with each LED is also proposed, which is cost-effective and suitable for IC process. A dual-loop control approach, which contains inner control loop and outer control loop to shape input current and to regulate output voltage, is also presented. In LED panel, the current of each LED string is sensed and controlled to accomplish current sharing and dimming feature. A 100 W prototype is designed, analyzed, and implemented. Simulations and practical results have demonstrated the feasibility of the single-stage Sepic-type LED driver and verified the aforementioned functions.

2. Power Stage Configuration

For high mains voltage or in low output voltage application, in general a Boost-type PFC is cascaded with a full-wave rectifier in the input and a step-down dc/dc converter in the output, as shown in Figure 1. The PFC stage shapes a high-crest-factor current caused by the full-wave rectifier into a purely sinusoidal waveform in phase with line voltage. However, the input voltage also is boosted. Therefore, it is required that a dc/dc converter is adopted to drop voltage for dc load. Power is processed by two stages, a PFC and a dc/dc converter, lowering overall efficiency and increasing cost. To release the mentioned drawbacks, a single-stage step-down PFC is adopted to simplify the structure of power-conversion stage, as shown in Figure 2, in which the PFC stage performs power factor correcting as well as steps down its input voltage to a desired level. In this paper, a dsPIC-based Sepic-type configuration is presented to serve as the single-stage step-down PFC for HB-LED driving, as shown in Figure 3. Figure 4 shows the corresponding main-stage schematic, in which the diodes 𝐷₅ and 𝐷₆ are introduced to prevent opposite current from flowing through inductors 𝐿₁ and 𝐿₂, respectively. In Figure 4, the two separate inductors 𝐿₁ and 𝐿₂ can be coupled magnetically. In addition, a proposed soft-switching cell, including an active switch 𝑄₂, an inductor 𝐿_𝑟,  and a capacitor 𝐶_𝑟, to achieve zero-voltage switching (ZVS) feature, is embedded into the power stage to reduce switching loss. Figure 5 is the derived single-stage coupled-inductor soft-switching Sepic-type HB-LED driver.

Figure 1 

A PFC stage cascaded with a full-wave rectifier in the input and a step-down dc/dc converter in the output.

Figure 2 

A block diagram representing single-stage step-down PFC.

Figure 3 

A block diagram representing that Sepic-type converter serves as PFC for LED lighting application.

Figure 4 

The main-stage schematic of a Sepic-type PFC.

Figure 5 

The proposed single-stage coupled-inductor soft-switching Sepic-type HB-LED driver.

3. Operation Principle of Power Stage

In Figure 5, while the soft-switching Sepic-type HB-LED driver operates in boundary conduction mode and with peak current control, a high power factor can readily be achieved. As a result, the envelope of the input current will follow the shape of line voltage to be sinusoidal, leading to unity power factor. As the resonant frequency of the soft-switching cell is much higher than switching frequency of main power circuit, over a switching cycle the operation of the driver can be divided into eight modes. Figure 6 is the corresponding circuits, and the related conceptual key waveforms are shown in Figure 7. The eight operation modes during a switching period are discussed as follows.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

Figure 6 

Equivalent circuits corresponding to the eight operation modes: (a) mode 1, (b) mode 2, (c) mode 3, (d) mode 4, (e) mode 5, (f) mode 6, (g) mode 7, and (h) mode 8.

Figure 7 

The related conceptual key waveforms.

(1) Mode 1 (𝑡₀≤𝑡<𝑡₁, Figure 6(a))
During this time interval, switch 𝑄₁ is on and 𝑄₂ off. The inductor currents of 𝑖_𝐿1 and 𝑖_𝐿𝑟 are linearly built, and the capacitor 𝐶₂ dumps energy to inductor 𝐿₂ by the way of 𝐿_𝑟, 𝑄₁, and 𝐷₆. At the same time, the capacitor 𝐶₃ supplies power for load. The time constant determined by capacitance of 𝐶₃ and load resistance is much larger than switching period so that output voltage 𝑣_𝑜 can be regarded as a constant. At time 𝑡=𝑡₁, this mode is ended and 𝑄₂ is turned off. In mode 1, the voltage across the resonant inductor, 𝑣_𝐿𝑟 can be calculated by 𝑣_𝐿𝑟=𝑣_𝐶1−𝑉_𝐷5−𝑉_𝐷𝑆1,on⋅𝐿_𝑟𝐿₁+𝐿_𝑟, (3.1) in which 𝑣_𝐶1 expresses rectified half sine wave, 𝑉_𝐷5 is the cut-in voltage of diode 𝐷₅, and 𝑉_𝐷𝑆1,on stands for the turn-on voltage across switch 𝑄₁. Then, inductor current 𝑖_𝐿𝑟 is determined as follows: 𝑖_𝐿𝑟(𝑡)=𝑖_𝐿𝑟(0)+^𝑡₀𝑣_𝐶1𝑡^′−𝑉_𝐷5−𝑉_𝐷𝑆1,on𝐿_𝑟+𝐿₁𝑑𝑡^′. (3.2) In (3.2), the initial value of inductor current 𝑖_𝐿𝑟(0) is found by the end of mode 8.

(2) Mode 2 (𝑡₁≤𝑡<𝑡₂, Figure 6(b))
The switch 𝑄₁  is turned off at 𝑡₁. The inductor 𝐿₁ discharges through the path of 𝐷₅, resonant inductor 𝐿_𝑟, and parasitical capacitor 𝐶_𝑏1. Meanwhile, the capacitor 𝐶₂ still dumps energy to 𝐿₂, and dc load draws power from 𝐶₃. Since typical value of 𝐶_𝑏1 is far smaller than the capacitance of 𝐶₂, the voltage 𝑣_𝐷𝑆1 across 𝐶_𝑏1 increases rapidly. Applying KVL to the loop, 𝐶₂-𝐿_𝑟-𝑄₁-𝐷₆-𝐿₂, one can obtain the following equivalent: 𝑣_𝐶2−𝐿_𝑟𝑑𝑖_𝐿𝑟𝑑𝑡−𝑣_𝐷𝑆1−𝑉_𝐷6−𝐿₂𝑑𝑖_𝐿𝑟𝑑𝑡=0, (3.3) in which 𝑉_𝐷6 is the cut-in voltage of diode 𝐷₆. Rearranging (3.3) yields 𝑖_𝐿𝑟(𝑡)=𝑖_𝐿𝑟𝑡₁+1𝐿_𝑟+𝐿₂^𝑡_𝑡1𝑣_𝐶2𝑡^′−𝑣_𝐷𝑆1−𝑉_𝐷6𝑑𝑡^′. (3.4) The 𝑖_𝐿𝑟(𝑡₁) is the initial value of 𝑖_𝐿𝑟 at mode 2, which can be found by (3.2). At 𝑡=𝑡₂, the voltage 𝑣_𝐷𝑆1 reaches 𝑣_𝐶2+𝑣_𝑜 and this mode is terminated.

(3) Mode 3 (𝑡₂≤𝑡<𝑡₃, Figure 6(c))
During this time interval, inductors 𝐿₁ and 𝐿_𝑟 still discharge energy, and voltage 𝑣_𝐷𝑆1 increases. The diode D₇ starts conducting, and the voltage across 𝐿₂ is equal to output voltage 𝑣_𝑜. Therefore, 𝐿₂ dumps energy to the output, and the inductor current 𝑖_𝐿2 is expressed by 𝑖_𝐿2(𝑡)=−𝑣_𝑂𝐿₂𝑡−𝑡₂+𝑖_𝐿2𝑡₂. (3.5) The capacitor 𝐶_𝑏1 will be charged to 𝑉_stress1, which is also the voltage stress of 𝑄₁. That is, 𝑉_stress1=𝑣_𝐶𝑟+𝑣_𝐶1−𝑣_{𝐿1𝑡=𝑡3}. (3.6)

(4) Mode 4 (𝑡₃≤𝑡<𝑡₄, Figure 6(d))
Both inductors 𝐿₁ and 𝐿₂ release energy continuously but capacitor 𝐶₂ charges. The parasitical capacitor of switch 𝑄₂ starts dumping energy by the way of 𝐶_𝑟 and 𝐿_𝑟 until 𝑣_𝐷𝑆2 drops to zero. The resonant frequency of the loop 𝐿_𝑟-𝐶_𝑏2-𝐶_𝑟 and the voltage across 𝑄₂ can be found as follows, respectively: 𝑓_𝑟,mode4=12𝜋𝐶_𝑏2+𝐶_𝑟𝐿_𝑟⋅𝐶_𝑏2⋅𝐶_𝑟,𝑣_𝐷𝑆2(𝑡)=𝑣_𝐶𝑏2𝑡₃cos2𝜋𝑓_𝑟,mode4𝑡−𝑡₃+𝑖_𝐿𝑟𝑡₃𝐿_𝑟⋅𝐶_𝑏2⋅𝐶_𝑟𝐶_𝑏2+𝐶_𝑟sin2𝜋𝑓_𝑟,mode4𝑡−𝑡₃. (3.7)

(5) Mode 5 (𝑡₄≤𝑡<𝑡₅, Figure 6(e))
The body diode of 𝑄₂ conducts, and inductor 𝐿_𝑟 resonates with 𝐶_𝑟. The resonant frequency in the soft-switching cell during this mode is 𝑓_𝑟,mode5=12𝜋𝐿_𝑟⋅𝐶_𝑟, (3.8) In addition, the following relationship holds: 𝐿_𝑟𝑑𝑖_𝐿𝑟1𝑑𝑡=−𝐶_𝑟^𝑡_𝑡4𝑖_𝐿𝑟𝑡^′𝑑𝑡^′−𝑣_𝐶𝑟𝑡₄−𝑉_𝐷𝑏2. (3.9) The 𝑉_𝐷𝑏2 is the voltage drop on the body diode 𝐷_𝑏2. According to (3.9), resonant inductor current 𝑖_𝐿𝑟 can be obtained by: 𝑖_𝐿𝑟(𝑡)=𝑖_𝐿𝑟𝑡₅cos𝑡−𝑡₅𝐿_𝑟⋅𝐶_𝑟−𝑉_𝐶𝑟𝑡₅𝐶_𝑟𝐿_𝑟sin𝑡−𝑡₅𝐿_𝑟⋅𝐶_𝑟. (3.10)
During this time interval, switch 𝑄₂ is tuned on with ZVS. Operation of the driver enters into next mode as the current 𝑖_𝐿𝑟 decreases to zero.

(6) Mode 6 (𝑡₅≤𝑡<𝑡₆, Figure 6(f))
The energy stored in resonant capacitor 𝐶_𝑟 is dumped to 𝐿_𝑟 via 𝑄₂. As a result, the current 𝑖_𝐿𝑟 increases negatively. In this time period, inductors 𝐿₁ and 𝐿₂ release energy but 𝐶₂ charges. At 𝑡=𝑡₆, 𝑄₂ is turned off and this mode is terminated.

(7) Mode 7 (𝑡₆≤𝑡<𝑡₇, Figure 6(g))
Switches 𝑄₁ and 𝑄₂ are off. The stored energy in the parasitical capacitor 𝐶_𝑏1 is drawn by inductor 𝐿_𝑟 and 𝑣_𝐷𝑆1 decreases. This mode ends when 𝑣_𝐷𝑆1 drops to zero. In this mode, the inductor 𝐿_𝑟 resonates with 𝐶_𝑏1 under the frequency of 𝑓_𝑟,mode7=12𝜋𝐿_𝑟⋅𝐶_𝑏1. (3.11)

(8) Mode 8 (𝑡₇≤𝑡<𝑡₈, Figure 6(h))
The energy stored in 𝐿_𝑟 is discharge by the way of 𝐶₂, 𝐷₇, 𝐶₃, and 𝐷_𝑏1. In this time interval, switch 𝑄₁ is triggered. This mode is terminated while 𝑖_𝐿1 equals zero. A complete switching cycle is ended at 𝑡=𝑡₈, at which switch 𝑄₁ has been turned on again.

4. Control of Driver

The proposed HB-LED driver not only steps down input voltage but also performs power factor correcting and functions as dimming feature. Dual-loop control and average-current control are adopted to achieve power factor correction and to regulate HB-LED current, respectively.

4.1. Control of Power Factor Correction

Figure 8 shows the block diagram of the dual-loop control. Zero-crossing point of the line voltage is detected by the zero-crossing detector, and, then, the sine-wave generator produces a unity sine wave in phase with the line voltage. In the dual-loop control, output voltage is fed back and compared with reference 𝑉_ref for determining the amplitude of current command. Meanwhile, input current is sensed and compared with current command for the determination of appropriate control signals driving 𝑄₁ and 𝑄₂. With the dual-loop control, input current shaping and output voltage regulating are readily accomplished over universal line-voltage range.

Figure 8 

A block diagram to represent the control of power factor correction.

The driver operates in boundary conduction mode to perform power factor correcting. Therefore, on-time interval 𝑇_on of the main switch 𝑄₁ within one switching cycle can be represented as 𝑇_on=𝑖_𝐿1,peak𝑣_𝐶1⋅𝐿₁+𝐿_𝑟. (4.1) The 𝑖_𝐿1,peak stands for peak value of inductor current through 𝐿₁ and is obtained from 𝑖_𝐿1,peak=2𝐼_PKsin2𝜋𝑓_𝐿𝑡. (4.2) In (4.2), 𝑓_𝐿 is the line frequency and 𝐼_PK expresses the amplitude of line current. In addition, off-time interval 𝑇_off of the main switch 𝑄₁ within one switching cycle is found by 𝑇_off=𝑖_𝐿1,peak𝑣_𝐶2+𝑣_𝑜−𝑣_𝐶1⋅𝐿₁. (4.3) Suppose that voltage drop on the input diodes can be neglected. Thus, 𝑣_𝐶1 can be expressed as 𝑣_𝐶1=𝑉_𝑃sin2𝜋𝑓_𝑠𝑡, (4.4) where 𝑉_𝑃 is the amplitude of line voltage. From (4.1)–(4.4), determination for 𝑇_on and 𝑇_off of a control signal can be further derived and becomes 𝑇_on=2𝐼_PK𝑉_𝑃⋅𝐿₁+𝐿_𝑟,𝑇_off=2𝐼_PKsin2𝜋𝑓_𝐿𝑡𝑣_𝐶2+𝑣_𝑜−𝑉_𝑃sin2𝜋𝑓_𝐿𝑡⋅𝐿₁. (4.5) Since the switching frequency of the driver, 𝑓_sw, is 𝑓_sw=1𝑇_on+𝑇_off, (4.6) with the relationships of (4.5), expression for 𝑓_sw is rewritten as 𝑓_sw=𝑉_𝑃𝑣_𝐶2+𝑣_𝑜−𝑉_𝑃sin2𝜋𝑓_𝐿𝑡2𝐼_PK𝑣_𝐶2+𝑣_𝑜𝐿₁+𝐿_𝑟−𝐿₁+𝐿_𝑟−1𝑉_𝑃sin2𝜋𝑓_𝐿𝑡. (4.7)

4.2. Dimming Control of HB-LED Panel

Each string current of HB-LED panel is controlled by current regulator to achieve current sharing and dimming feature. The current regulator mainly includes an active switch and a current sensor, as shown in Figure 9. String current is sensed, and, then, according to its average value the duty ratio of the active switch is determined so as to accomplish 400 Hz burst-mode current control. Consequently, string current can be controlled to achieve luminance balance and dimming feature. The associated average-current calculation and dimming signal determination are all-digital implementation, of which control block diagram is illustrated in Figure 10.

Figure 9 

The HB-LED panel with current regulators and by-pass circuits.

Figure 10 

A block diagram to represent the control for LED panel.

In Figure 9, duty ratio of the active switch in the jth LED string, 𝐷_dim,𝑗, can be expressed as 𝐷_dim,𝑗=𝑇_dim,on,𝑗𝑇_dim, (4.8) where 𝑇_dim denotes the period of dimming signal and 𝑇_dim,on,𝑗 is the on-state time interval of the active switch in the jth LED string. In Figure 10, average value of the jth-string sensed current is calculated by 𝐼_𝑠,𝑗=1𝑇_dim^{𝑇dim,on,𝑗}₀𝑖_𝑠,𝑗(𝑡)𝑑𝑡. (4.9) Additionally, while the jth active switch is closed, a corresponding current through the jth LED string has to be 𝐼_LED,on,𝑗=𝑣_𝑂−𝑁_𝑗⋅𝑉_𝑓,LED𝑁_𝑗⋅𝑅_𝑑. (4.10) In (4.10), 𝑁_𝑗 is the total number of LEDs in the jth string; 𝑉_𝑓,LED and 𝑅_𝑑 are the forward voltage and equivalent series resistance of LED, respectively. Since 𝐼_𝑠,𝑗 can be also evaluated by 𝐼_𝑠,𝑗=𝐷_dim,𝑗⋅𝐼_LED,on,𝑗, (4.11) then, from (4.9)-(4.11) the following equivalent holds: 𝐷_dim,𝑗=𝑁_𝑗⋅𝑅_𝑑𝑇_dim𝑣_𝑜−𝑁_𝑗⋅𝑉_𝑓,LED^{𝑇dim,on,𝑗0}𝑖_𝑠,𝑗(𝑡)𝑑𝑡. (4.12) Based on (4.12), to determine 𝐷_dim,𝑗, the values of 𝑅_𝑓 and 𝑉_𝑓,LED should be given in advance, which leads to the determination error caused from the aging effect of LED. To avoid the drawback, the difference between the average sensed current 𝐼_𝑠,𝑗 and a reference current 𝐼_ref is amplified and then compared with a triangular waveform so as to fulfill pulse-width-modulation (PWM) current control, as shown in Figure 10. The corresponding control law can be expressed as follows: 𝐷_dim,𝑗=𝑉_tri,peak/2+𝐾_𝑝𝐼_ref−𝐼_𝑠,𝑗𝑉_tri,peak, (4.13) where 𝑉_tri,peak is the peak value of the triangular waveform and 𝐾_𝑝 stands for a constant. The 𝐷_dim,𝑗 is in the range of 0-1.

In this paper, a by-pass circuit is also presented, which is in parallel with LED, as shown in Figure 9. While LED being out of order, it is triggered and provides an alternative path to continue string current. As the presented by-pass circuit conducts, voltage drop across its terminals is about 1 V. Compared with conventional single-zener-diode by-pass circuit, of which conduction voltage drop is larger than 3.3 V, the power dissipation of the presented by-pass circuit is much smaller than that of the conventional one.

5. Design Considerations

The inductances and capacitances, 𝐿₁, 𝐿₂, 𝐶₂, and 𝐶₃, influence the performances of the single-stage driver significantly. Determinations for 𝐿₁ and 𝐿₂ are presented as follows:𝐿₁=𝐿_𝑙1𝐿_𝑙2+𝐿_𝑚𝐿_𝑙1+𝑛²𝐿_𝑚𝐿_𝑙2𝐿_𝑙2−(𝑛−1)𝐿_𝑚,𝐿₂=𝐿_𝑙1𝐿_𝑙2+𝐿_𝑚𝐿_𝑙1+𝑛²𝐿_𝑚𝐿_𝑙2𝐿_𝑙1+𝑛(𝑛−1)𝐿_𝑚, (5.1) in which 𝑛 is the turns ratio of the coupled inductors, 𝐿_𝑚 denotes the magnetizing inductance, and 𝐿_𝑙1 and 𝐿_𝑙2 stand for leakage inductances of winding 1 and winding 2, respectively. In addition, the capacitances 𝐶₂ and 𝐶₃ are obtained by 𝐶₂=𝐿_𝑒Δ𝑉_𝐶1(max)⋅𝐼²_PK2⋅1𝑉_𝑜+√2𝑉_AC(min),𝐶₃=𝐼_𝑜2⋅𝜋⋅𝑓_𝐿⋅Δ𝑉_𝑜, (5.2) where 𝐿_𝑒 equals 𝐿_𝑙1//𝐿_𝑙2, 𝑉_𝑜 and Δ𝑉_𝑜 represent dc-bus voltage and its ripple component, in turn, and 𝑉_AC(min) expresses the rms value of the minimum line voltage. The peak value of the inductor current 𝑖_𝐿1 can also be expressed as follows: 𝑖_𝐿1,peak(𝑡)=𝑉_𝑃𝑇_onsin2𝑓_𝐿𝜋𝑡𝐿₁. (5.3) Then, the filtered input current is determined by 𝑖_{𝑠,filtered}(𝑡=2)𝑇_𝑠^𝑇𝑠₀^/2𝑖_𝐿1(𝑡)=𝑑𝑡2𝑉_𝑝𝑇_on𝑇_𝑠⋅𝐿₁+𝐿_𝑟𝑓_𝐿.⋅𝜋 (5.4) In addition, the power drawn from line voltage can be computed in the following: 𝑃_in=2𝑇_𝑠^𝑇𝑠₀^/2𝑣_𝑠(𝑡)⋅𝑖_{𝑠,filtered}(𝑡)=𝑑𝑡2𝑉²_𝑝𝑇_on+𝑇_𝑠𝐿₁+𝐿_𝑟𝑇_𝑠⋅𝐿₁+𝐿_𝑟𝑓_𝐿.⋅𝜋 (5.5)

In Figure 8, the output voltage 𝑣_𝑜 is divided by the two resistors, 𝑅_𝑚 and 𝑅_𝑠, with 1% accuracy such that the voltage 𝑣_𝑅𝑠 can be described as 𝑣_𝑅s=𝑣_𝑜𝑅_𝑠(1±1%)𝑅_𝑠(1±1%)+𝑅_𝑚().1±1% (5.6) Suppose that a 10-bit analog-to-digital converter (ADC) is used. Therefore, the ADC resolution is calculated as Resolution=SupplyVoltage=510-bitADC2¹⁰≅0.00488(V). (5.7) Thus, the maximum deviation of 𝑣_𝑅𝑠 after analog-to-digital conversion is 𝑣_{𝑅𝑠,conmax}=𝑣_𝑅𝑠±0.0048. (5.8) Accordingly, the deviation on the output voltage, Δ𝑣_𝑜,  can be found by Δ𝑣_𝑜𝑅=±0.0048^𝑠(1±1%)+𝑅_𝑚(1±1%)𝑅_𝑠().1±1% (5.9)

6. Simulations and Hardware Measurements

A prototype of the proposed HB-LED driver is built to demonstrate the theoretical analysis and to verify the feasibility, of which controller is implemented on a 16-bit disPIC-30F4011 chip. The adopted microcontroller comprises a 10-bit ADC with conversion rate up to 500 Ksps, 9 input channels, 6 PWM outputs, and 5 16-bit timers. It fulfills the controlling of power factor correction, current sharing, and dimming. The driver has been designed according to the following specifications:input voltage: 85∼265 V,output power: 100 W,output current: 1.75 A,output voltage: 58 V,LED: LUMILEDS 1.2 W/3.42 V/0.35 A,LED panel: 5 strings, 17 pieces in series for each string.Component values and important parameters are determined as:𝑄₂: IRF730 (400 V/5.5 A),𝑄₁: 17N80C3 (800 V/17 A),𝐿₁ = 1.2 mH, 𝐿₂= 0.77 mH, 𝐿_𝑟 = 0.1 mH,𝐶₁ = 0.1 𝜇F, 𝐶₂ = 0.25 𝜇F, 𝐶₃ = 100 𝜇F, and 𝐶_𝑟 = 0.05 𝜇F.Figure 11 is the waveforms of voltage and current of the main switch 𝑄₁, while Figure 12 shows the waveforms of 𝑄₂ in the soft-switching cell. From Figures 11 and 12, it can be observed that zero-voltage switching (ZVS) feature is achieved by the both switches 𝑄₁ and 𝑄₂. Figure 13 is the simulated waveform of the current 𝑖_𝐿1. Figure 14 shows the simulated line voltage and input current when mains voltage is 110 V. For 220 V mains input, the simulated line voltage and input current are shown in Figure 15. Figure 16 shows the hardware measurement of line voltage and input current while mains voltage is 110 V. From Figures 13–16, it can be found that a unity power factor is achieved by the single-stage HB-LED driver. Figure 17 shows the harmonics of the input current measured by PM3000 and then compared with IEC6100-3-2 class C. From Figure 17, it can be observed that the line current harmonics are much less than the requirements of the standard. Power factor and efficiency measurements are shown in Figures 18 and 19, in turn, illustrating that high power factor and efficiency can be achieved by the single-stage HB-LED driver.

Figure 11 

Voltage and current waveforms of switch 𝑄1.

Figure 12 

Voltage and current waveforms of switch 𝑄2.

Figure 13 

The current waveform of the inductor 𝐿1.

Figure 14 

Line voltage and input current when mains voltage is 110 V.

Figure 15 

Line voltage and input current when mains voltage is 220 V.

Figure 16 

Practical results of line voltage and input current.

Figure 17 

Measured input current harmonics.

Figure 18 

Power factor measurement over universal-line input range.

Figure 19 

Measured efficiency over universal-line input range.

7. Conclusion

This paper has proposed a single-stage Sepic-type soft-switching HB-LED driver with coupled inductor for universal line input. The proposed driver not only can perform power factor correcting but also achieve zero-voltage switching feature and step down input voltage directly. Consequently, a unity power factor is obtained and efficiency is improved. In the driver, its output voltage can be much smaller than the ac-side voltage, reducing component stresses significantly. Therefore, the driver is suitable for the applications of high-line voltage and/or low output voltage. To drive LED panel, an all-digital controller is also presented for power factor correcting, dc-bus voltage regulating, current sharing, and LED dimming, which is implemented on a 16-bit disPIC chip. A prototype of the designed single-stage driver to ballast 100 W 58 V HB-LED panel has been built. The simulations and practical measurements have verified the feasibility and features of the single-stage HB-LED driver.