Difference-Equation-Based Digital Frequency Synthesizer

Abstract

This paper presents a novel algorithm and architecture for digital frequency synthesis (DFS). It is based on a simple difference equation. Simulation results show that the proposed DFS algorithm is preferable to the conventional phase-locked-loop frequency synthesizer and the direct digital frequency synthesizer in terms of the spurious-free dynamic range (SFDR) and the peak-signal-to-noise ratio (PSNR). Specifically, the results of SFDR and PSNR are more than 186.91 dBc and 127.74 dB, respectively. Moreover, an efficient DFS architecture for VLSI implementation is also proposed, which has the advantage of saving hardware cost and power consumption.

1. Introduction

Many modern devices, for example, radio receivers, ADSL (Asymmetric Digital Subscriber Line), XDSL (X Digital Subscriber Line), 3G/4G mobile phones, walkie-talkies, CB radios, satellite receivers, and GPS systems, require frequency synthesizers with fine resolutions, fast channel switching, and large bandwidths. There are two types of frequency synthesizer available: phase-locked loop (PLL) and direct digital frequency synthesis (DDFS).

PLL is a control system, which generates an output signal with phase matched that of the input reference signal. Figure 1 shows the conventional PLL frequency synthesizer consisting of a phase detector, a charge bump, a lowpass filter, a voltage control oscillator, and a frequency divider [1–8]. The lower frequency signal, 𝐹_div, obtained by dividing the output signal via the frequency divider, is compared with the reference signal, 𝐹_ref, in the phase detector to generate an error signal, which is proportional to the phase difference. The charge bump converts the error signal pulse into analog current pulses, which are then integrated by using the lowpass filter, and drives the voltage-controlled oscillator to obtain the desired frequency.

Figure 1 

Block diagram of the conventional PLL system.

The commonly used architecture of DDFS [9] shown in Figure 2 consists of a phase accumulator, a sine/cosine generator, a digital-to-analog converter (DAC), and a lowpass filter (LPF). It takes two inputs: a reference clock and a 𝑣-bit frequency control word (FCW). In each clock cycle, the phase accumulator integrates FCW with periodical overflow to produce an angle in the range of [0,2𝜋), the sine/cosine generator computes its sinusoidal value, which in practice is implemented digitally and, therefore, follows by DAC and LPF [10–23]. Various fractional-order ideal filters and fractional oscillators were proposed in [24–29].

Figure 2 

Block diagram of the conventional DDFS architecture.

Instead of using the conventional methods above, we propose a novel digital frequency synthesis (DFS) algorithm based on a simple difference equation. The rest of the paper is organized as follows. In Section 2, a novel DFS algorithm is proposed. In Section 3, the VLSI (very large-scale integration) digital frequency synthesizer is presented. In Section 4, the FPGA implementation and the performance evaluation are given. Conclusion can be found in Section 5.

2. The Proposed DFS Algorithm

The difference equation of DFS is as follows: 𝑦[𝑛−2]−2𝑎₁𝑦[𝑛−1]+𝑎₂𝑦[𝑛]=𝑥[𝑛]. (2.1) Thus, we have the following characteristic equation: 𝑧⁻²−2𝑎₁𝑧⁻¹+𝑎₂=0. (2.2) The eigen-functions of (2.2) are represented as 𝑧_1,2=𝑟𝑒^±𝑗𝜃. (2.3) The ZIR (zero-input response) of DFS can be written as ZIR=𝑟^𝑛𝐵₁cos(𝑛𝜃)+𝐵₂sin(𝑛𝜃), (2.4) where 𝐵₁ and 𝐵₂ are determined by initial conditions, and 𝑛=0,1,2,….

For DFS with sine wave generator, we have 𝑟=1,𝐵₁=0,𝐵₂=1,ZIR=sin(𝑛𝜃). (2.5) The eigen-functions of DFS are therefore as follows: 𝑧_1,2=𝑒^±𝑗𝜃=cos𝜃±𝑗sin𝜃=𝑐±𝑗𝑑. (2.6) Thus, the characteristic equation can be expressed as 𝑧⁻²−2𝑐𝑧⁻¹+𝑐²+𝑑²=0, (2.7) where 𝑐²+𝑑²=1.

Equation (2.7) could be rewritten as 𝑧⁻²−2𝑐𝑧⁻¹+1=0, (2.8) and the transfer function of DFS can be derived as 𝐻(𝑧)=1𝑧⁻²−2𝑐𝑧⁻¹+1. (2.9) According to (2.9), the corresponding difference equation could be derived as 𝑦[𝑛]=𝑥[𝑛]−𝑦[𝑛−2]+2𝑐⋅𝑦[𝑛−1], (2.10) where 𝑦[0]=𝐵₁𝑦[1]=0,=−𝐵₁cos𝜃+𝐵₂sin𝜃=𝑑. (2.11)

As one can see, a rotation of angle 𝜙 in the circular coordinate system can be obtained by performing a sequence of microrotations in an iterative manner. In particular, a vector can be successively rotated through the use of a sequence of predetermined step angles: 𝛼(𝑖)=tan⁻¹(2^−𝑖). This technique can be applied to generate many elementary functions, in which only simple adders and shifters are required. Thus, the well-known coordinate rotation digital computer (CORDIC) algorithm can be used for the DFS applications. The conventional CORDIC in the circular coordinate system is as follows [36–39]: 𝑢(𝑖+1)=𝑢(𝑖)−𝜎(𝑖)2^−𝑖𝑣(𝑖),𝑣(𝑖+1)=𝑣(𝑖)+𝜎(𝑖)2^−𝑖𝑢(𝑖),𝑤()(𝑖)(𝑖)𝛼(𝑖),𝛼(𝑖)𝑖+1=𝑤−𝜎=tan⁻¹2^−𝑖, (2.12) where 𝜎(𝑖)∈{−1,+1} denotes the direction of the 𝑖th microrotation, 𝜎_𝑖=sign(𝑤(𝑖)) with 𝑤(𝑖)→0 in the vector rotation mode, 𝜎_𝑖=−sign(𝑢(𝑖))⋅sign(𝑣(𝑖)) with 𝑣(𝑖)→0 in the angle accumulated mode, the corresponding scale factor 𝑘(𝑖) is equal to 1+𝜎²(𝑖)2^−2𝑖, and 𝑖=0,1,…,𝑙−1. The product of all scale factors after 𝑙 microrotations is given by 𝐾₁=^𝑛−1_𝑖=0𝑘(𝑖)=^𝑛−1_𝑖=0√1+2^−2𝑖. (2.13) In the vector rotation mode, sin𝜙 and cos𝜙 can be obtained, where the initial value (𝑢(0),𝑣(0))=(1/𝐾₁,0). In principle, 𝑢_out and 𝑣_out can be computed from the initial value (𝑢_in,𝑣_in)=(𝑢(0),𝑣(0)) by using the following equation: 𝑢_out𝑣_out=𝐾₁cos𝜙−sin𝜙𝑢sin𝜙cos𝜙𝑣ⁱⁿ_in. (2.14)

In order to evaluate the sinusoidal parameters: 𝑐 and 𝑑 for the proposed digital frequency synthesizer, the inputs of the CORDIC processor are 𝑢_in=1/𝐾₁, 𝑣_in=0, and 𝑤_in=𝜃 as shown in Figure 3.

Figure 3 

The CORDIC arithmetic for the proposed digital frequency synthesizer.

3. Proposed Architecture for Digital Frequency Synthesizer

In this section, the architecture and the terminology associated with the proposed digital frequency synthesizer are presented. Our scheme is based on the proposed DFS algorithm combined with a CORDIC processor. It consists mainly of the radian converter, the CORDIC processor, and the sine generator as shown in Figure 4.

Figure 4 

The proposed digital frequency synthesizer.

Figure 5 shows the radian converter. It is a constant multiplier, which converts the input signal into radians. Figure 6 shows the CORDIC processor, which evaluates the sinusoidal value and consists of three adders and two shifters.

Figure 5 

The radian converter.

Figure 6 

The CORDIC processor (LUT: Lookup table).

Figure 7 shows the architecture of sine generator, which is the core of the proposed digital frequency synthesizer. It consists of one multiplier, one adder, and two latches only.

Figure 7 

The sine generator.

The key terminologies associated with the proposed digital frequency synthesizer are as follows.

3.1. Output Frequency

The output frequency of the proposed digital frequency synthesizer is determined by the coefficients 𝑑 and 𝑐, since 𝜃=𝜔𝑇_𝑠=tan⁻¹𝑑𝑐,𝐹_𝑜=12𝜋⋅tan⁻¹𝑑𝑐⋅𝐹_𝑠. (3.1)

3.2. Frequency Resolution

For 𝑚-bit digital frequency synthesizer, the minimum change of the output frequency Δ𝐹_𝑜,min is expressed as Δ𝐹_𝑜,min=12𝜋⋅tan⁻¹2^{−(𝑚−1)}⋅𝐹_𝑠. (3.2)

3.3. Bandwidth

The bandwidth of digital frequency synthesizer is defined as the difference between the highest and lowest attainable output frequencies, which are expressed as follows: 𝐹_𝑜,max=12𝜋⋅tan⁻¹(1)⋅𝐹_𝑠,𝐹_𝑜,min=12𝜋⋅tan⁻¹2^{−(𝑚−1)}⋅𝐹_𝑠. (3.3)

3.4. Peak Signal-to-Noise Ratio (PSNR)

A good direct digital frequency synthesizer should have an output signal with low noise, which can be evaluated by using the following signal-to-noise-ratio (PSNR) measured in dB: PSNR=20log255√MSE, (3.4) where MSE is the mean square error.

3.5. Spurious-Free Dynamic Range (SFDR)

The spurious-free dynamic range (SFDR) is defined as the ratio of the amplitude of the desired frequency component to that of the largest undesired frequency component at the output of a DDFS. It is expressed in decibels (dBc) as follows:𝐴SFDR=20log^𝑝𝐴_𝑠=20log𝐴_𝑝−20log𝐴_𝑠, (3.5) where 𝐴_𝑝 is the amplitude of the desired frequency component, 𝐴_𝑠 is the amplitude of the largest undesired frequency component, and the higher the better.

4. FPGA Implementation of Digital Frequency Synthesizer

In this section, the proposed high-performance architecture of digital frequency synthesizer is presented. Figure 8 depicts the system block diagram. The PSNR and SFDR of the proposed digital frequency synthesizer at various word lengths at 100 MHz sampling rate and the maximum output frequency 12.5 MHz are shown in Figures 9 and 10, respectively.

Figure 8 

The proposed digital frequency synthesizer.

Figure 9 

The PSNR of the proposed digital frequency synthesizer at various word lengths (100 MHz sampling rate and the maximum output frequency 12.5 MHz).

Figure 10 

The SFDR of the proposed digital frequency synthesizer at various word lengths (100 MHz sampling rate and the maximum output frequency 12.5 MHz).

The platform for architecture development and verification has also been designed and implemented to evaluate the development cost. The proposed architecture of digital frequency synthesizer has been implemented on the field programmable gate array (FPGA) emulation board [40]. The FPGA has been integrated with the microcontroller (MCU) and I/O interface circuit (USB 2.0) to form the architecture development and verification platform.

Figure 11 depicts the block diagram and circuit board of the architecture development and evaluation platform. In which, the microcontroller reads data and commands from PC and writes the results back to PC via USB 2.0 bus; the FPGA implements the proposed architecture of digital frequency synthesizer. The hardware code in portable hardware description language runs on PC with the logic circuit simulator [41] and FPGA compiler [42]. It is noted that the throughput can be improved by using the proposed pipelined architecture while the computation accuracy is the same as that obtained by using the conventional architecture with the same word length. Thus, the proposed digital frequency synthesizer improves the power consumption and performance significantly. Moreover, all the control signals are internally generated onchip. The proposed digital frequency synthesizer provides a high-performance sinusoid waveform.

Figure 11 

Block diagram and circuit board of the architecture development and verification platform.

5. Conclusion

In this paper, we present a novel digital frequency synthesizer based on a simple difference equation with pipelined data path. Circuit emulation shows that the proposed high-performance architecture has the advantages of high precision, high data rate, and simple hardware. For 16-bit digital frequency synthesizer, the PSNR and SFDR obtained by using the proposed architecture at the maximum output frequency are 127.74 dB and 186.91 dBc, respectively. As shown in Table 1, the proposed digital frequency synthesizer is superior to the previous works in terms of SFDR, PSNR, and hardware [18, 30–35]. The proposed digital frequency synthesizer designed by portable hardware description language is a reusable IP, which can be implemented in various VLSI processes with trade-offs of performance, area and power consumption.

Table 1 

Comparisons between the proposed DFS and other related works.

Acknowledgment

The National Science Council of Taiwan, under Grants NSC100-2628-E-239-002-MY2, supported this work.