Mathematical Problems in Engineering

Volume 2013 (2013), Article ID 691740, 23 pages

http://dx.doi.org/10.1155/2013/691740

## Electrical Network Functions of Common-Ground Uniform Passive *RLC* Ladders and Their Elmore’s Delay and Rise Times

^{1}Department of Physics & Electrical Engineering, School of Mechanical Engineering, University of Belgrade, Kraljice Marije 16, 11120 Belgrade, Serbia^{2}Department of General Electrical Engineering, School of Electrical Engineering, University of Belgrade, Bulevar Kralja Aleksandra 73, 11000 Belgrade, Serbia^{3}Department of Telecommunications, School of Electrical Engineering, University of Belgrade, Bulevar Kralja Aleksandra 73, 11000 Belgrade, Serbia

Received 18 February 2013; Accepted 19 May 2013

Academic Editor: Xinkai Chen

Copyright © 2013 D. B. Kandić et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

In the paper are presented the expressions for all network functions of common-ground, uniform passive ladders having, in general, complex terminations at both their ends. The Elmore's delay and rise times calculated for selected types of *RLC* ladders have indicated their slight deviation from delay and rise times obtained according to their classical definitions. For common-ground, integrating type *RC* ladder with voltage-step input, the Elmore's delay- and rise-times are produced in closed-form, both for ladder nodes and points. Furthermore, it is proposed a particular common-ground, uniform *RLC* ladder being amenable to application as delay line for pulsed and analog input signals. For this ladder, the Elmore's delay and rise times relating to their node voltages are produced in a closed-form, enabling thus with the realization of artificial (a) pulse delay line with arbitrarily and independently specified overall Elmore's delay and rise times and (b) true delay line with arbitrarily specified delay time for frequency bounded analog and/or pulsed input signals. In cases (a) and (b), precise procedures are formulated for calculation of ladder length and of all its *RLC* parameters. The obtained results are illustrated with several practical examples and are, also, verified through PSPICE simulation.

#### 1. Introduction

Modeling of digital MOS circuits by *RC* networks has become a well-accepted practice for estimating delays [1–6]. In digital integrated circuits, signal propagation delay through conducting paths with distributed resistance and capacitance is frequently a significant part of the total delay. These conducting paths, or “interconnections,” can be modeled quite accurately by nonuniform, branched *RC* ladder networks, also known as “*RC* trees” [3]. Computationally simple bounds for signal delay in linear *RC *tree networks were found in [3] and have been used in several practical MOS timing analyzers reported in [6], but certain circuits used in MOS logic cannot be modeled as *RC* trees since they contain one or more closed loops of resistors, and these general *RC *networks are being referred to as “*RC *meshes”. In these networks, the time delay defined according to Elmore [7] is proved to be the valid estimate, and this fact has been used in [5] to advantage in an approach to MOS timing analysis of general *RC* networks containing *RC *meshes. Simple closed-form bounds for signal propagation delay in linear *RC* tree models for MOS interconnections derived in [3] are, also, valid for the more general class of linear networks known as *RC* meshes, which are useful as models for portions of MOS logic circuits that cannot be represented as *RC *trees [6].

Elmore’s delay is an extremely popular timing-perfomance metric which is used at all levels of electronic circuit design automation, particularly for *RC* tree analysis. The widespread usage of this metric is mainly attributable to its property of being a simple analytical function of circuit parameters, and its drawbacks are the uncertainty of accuracy and restriction to being the estimate only for the step-response delay. An extension of Elmore’s delay definition has been proposed in [8] to accommodate the effect of nonunit-step (slow) excitations and to handle multiple sources of excitation, in order to show that delay estimation for slow excitations is no harder than for the unit-step input. In [9] it has been shown that this extension of Elmore’s delay time offers a provision to deal with slow varying excitations in timing analysis of MOS pass transistor networks. In addition, in [10] it has been reported that Elmore’s delay is an absolute upper bound on the actual 50% delay of an *RC* tree response. Also in [10], it has been proved that this bound holds for input signals other than steps and that actual delay asymptotically approaches to Elmore’s delay as the input signal rise-time increases. It has been emphasized in [11] that *RC* tree step responses always are monotonic, and this is why Elmore’s definitions of both delay and rise time [7] are applicable on complex *RC* tree networks.

In this paper we will firstly derive the general, closed-form expressions for input and transfer functions of common-ground, uniform, and passive ladders with complex double terminations, making a distinction between the signal transfer to ladder nodes and to its points. Then, simplifications of the obtained results are produced for ladders with seven specific pairs of complex double terminations being interesting from the practical point of view. Thereafter, for a uniform, common-ground *RLC *ladder with (a) a relation between its parameters resembling to analogous relation between per-unit-length parameters of distortionless transmission line and (b) symmetric, resistive double termination resembling to characteristic impedance of distortionless line [12], it will be shown that its Elmore’s delay and rise times for point voltage transmittances can be efficiently calculated (but not in the closed form) by using of the numerical scheme proposed herein. In this case, we will see that the obtained numerical values for Elmore’s times differ slightly from the delay and rise times obtained according to their classical definitions and by using PSPICE simulation when ladder is excited by a step voltage.

For the integrating type of distributed RC impedance, common-ground ladder as a model of two-wire line, it has been suggested that it might be used as a true pulse delay line [13], provided that, Schmitt triggers are used for reshaping the delayed and edge-distorted transmitted signals. This type of delay line with step-input excitation has already been thoroughly investigated in [14]—where Elmore’s delay time is given in closed form only for ladder nodes, and for Elmore’s rise time is offered a conjecture relating to its lower bound for overall network. Elmore’s rise times for all nodes of integrating, *RC *open-circuited ladder are given in closed form in [15] and the obtaining of Elmore’s delay and rise times both for nodes and points is discussed to some extent in [16]—for other types of open-circuited ladders. In this paper, we are going to formulate the explicit closed-form expressions for Elmore’s delay and rise times both for the node and point voltages of integrating open circuited, common-ground *RC *ladder and will conclude that this type of network is not recommendable for pulse delay line in its own right, since Elmore’s rise time of each point voltage is not less than the twice of its delay-time.

And finally, we will propose a type of uniform, common-ground *RLC* ladder amenable for application as delay line both for pulsed and/or analog input signals. Elmore’s delay and rise times of this ladder relating to the node voltage transmittances are produced in closed form, opening thus with the following possibilities in ladder realization:(i)for pulsed inputs, the overall Elmore delay and rise times may be specified arbitrarily,(ii)for pulsed inputs, the minimum ladder length (i.e., the minimum necessary number of sections) is calculated straightforwardly by using only the overall Elmore delay and rise times,(iii)the ladder *RL* parameters are calculated uniquely from the assumed nonminimal ladder length, overall Elmore delay time, and the assumed capacitance values,(iv)for realization of true delay for pulsed and/or analog input signals with arbitrary variation in time, minimum ladder length is calculated from the specified true delay time (which asymptotically tends to Elmore’s delay time when the number of sections tends to infinity) and maximum frequency in the spectrum of the signal being transmitted along the ladder purporting to represent delay line. And again, as in (iii), the ladder *RL* parameters are determined from the ladder length, overall ladder true delay time (being approximately equal to Elmore’s delay time), and the assumed capacitance values. The previous approach and obtained results are illustrated and verified with realization examples of large true delay time (=5 [ms]) for pulsed, sine, distorted sine, CAM, FM; and chirp frequency and sweep amplitude input signals.

Recall that in network synthesis the ladder topology is a preferable one, since it has very low sensitivity to variations of *RLC *parameters [16, 17].

#### 2. Network Functions of Common-Ground, Uniform, and Passive *RLC *Ladders

Consider a uniform, grounded, and passive *RLC *ladder in Figure 1 with identical sections, whose impedances and are *positive real rational functions* in complex frequency (). There on are denoted the Laplace transforms of the voltage excitation , and of the *point voltages * and currents , and and of *node voltages * and currents . The internal impedances of the voltage excitation (voltage generator) and the load are and , respectively. All the initial conditions associated to the network reactive (*LC*) elements are assumed to be zero.

For ladder in Figure 1, the mesh transform equations for its th section () read

The boundary values of voltages and currents in the set of matrix difference equations (1) are and . For , from (1) it immediately follows that Since the roots (say and ) of the characteristic equation corresponding to matrix appearing in (1), satisfy the relations and , then by taking for convenience and , we obtain . By using Cayley-Hamilton’s theorem we may put where the “constants” and are determined from system of equations and , whose solution is and .

By substituting and in (4) and bearing in mind that we finally obtain from (2) and (4) for that

Since uniform ladder sections are electrically reciprocal, then their characteristic impedance and the quantity can easily be produced in the form

For the ladder depicted in Figure 1, the complete set of the network immittance and voltage/current transmittance functions can be produced, by using the relations (2), (6), and (7):

Since , then the voltages and currents of impedances connecting the middle nodes of ladder sections () to common-node (Figure 1) are given as

Consider now the particular selection of , to investigate the generation of finite length, frequency-selecting ladders with various input and transfer immittances and voltage and current transmittances and specific ladder which can take the role of finite pulse delay line without pulse attenuation and with independently controlled pulse delay and rise times in Elmore’s sense [7], calculable in closed form. We will assume that impedances and are *rational positive real functions in *, so that they are realizable by passive transformerless* RLC *networks [17]. All network functions in (8) and (9) are *real rational functions in *, except , which must be *rational*,* positive real function in *, since it is the input immittance of *RLC *network.

*Case A ( **-arbitrary ** [ **])* (open-circuited ladder). From (8) and (9) it follows,

Since we have , then by Property 2 (Appendix A), (10) can be easily converted into real rational function of or of . Similarly, by Property 3 (Appendix A), (10) can be, also, easily converted into real rational function of or of . When and are one-element-kind impedances, the zeros and poles of both and can be easily determined in the closed form. Since by Property 3 and contain the same factor , then (11) can be, also, easily converted into real rational function, either of or of the complex frequency .

*Case B* ( []). In this case (10) and (11) simplify to

*Case C* (-*arbitrary * (short-circuited ladder)) From (8) and (9) it is obtained,
According to Properties 2 and 3, respectively, and (14) can be easily converted into real rational functions, either of or of the complex frequency . If and are one-element-kind impedances, the zeros and poles of both and can be determined straightforwardly in closed form. Now, since and/or , it can be seen from (15) that is, also, convertible into real rational function, either of or of the complex frequency , by using of both Properties 2 and 3.

*Case D* (). From (14) and (15) it readily follows that
By using of Properties 2 and 3 and , it can be seen from (16) and (17) that the network functions , , , *,* and can be easily converted into real rational functions, either of or of the complex frequency .

*Case E* (). From (8) and (9), after using the relations , and , it can be easily obtained that

*Case F* (). From (8) and (9), after using relations , and , it readily follows that

*Case G* (). From (7) it is easily obtained that , and . And from (8) and (9) it follows that

From (22) and (23) it can be seen that even when emf [with Laplace transform ] is pulsed, the node and point voltages with respect to common-ground (Figure 1) are reproduced faithfully and without delay but with geometrically progressive amplitude attenuation, regardless of the impedance .

It is clear that relations (7)–(9) offer many other possibilities for the selection of , , , and that lead to generation of versatile ladders realizing different types of frequency selective networks. An interesting one seems to be the common-ground *RLC *ladder realizing (a) pulse delay with independently selected Elmore’s delay and rise times and/or (b) true delay for either pulsed or analog frequency limited input signals. These topics will be considered in the following section.

#### 3. Elmore’s Delay and Rise Times for Selected Types of Common-Ground, Uniform *RLC *Ladders

Consider the ladder in Figure 1 having , , and . Suppose that it holds the relation , *similar* to the one associated with per-unit-length parameters of *distortionless transmission line* [18, 19]. Let us define the auxiliary parameter , and let us recast the network voltage transmittances describing the transfer of emf to the ladder *points* with voltages (Figure 1)—in the form suitable for calculating of Elmore’s delay and rise times [7] (Appendix B). Firstly, we should observe that the following holds:
and then by using (8) and the Properties 2 and 3, let us express the *point voltage transmittances * and in the following form:
As the calculation example of Elmore’s times, let us suppose for this type of ladder that the specified parameters are , [], [mH], [mS], and [F]. We firstly calculate [1/s], and [1/s], and then we recast and (25) in the following form:
where all “” and “” coefficients are positive. To apply Elmore’s definitions of delay and rise times (Appendix B) for all points in the ladder with zero initial conditions (Figure 1) and excited at with the step-voltage with amplitude ,
we *must* do the following.(i)Firstly, check that the point voltages have no overshoots, or eventually if they are present, overshoots must be less than 5% of those voltages steady state values [7]. For example, if we have assumed for ladder with sections that [V], then its voltage step-responses and the node response as well, obtained through PSPICE simulation and depicted in Figures 2 and 3 in the interval , reveal that Elmore’s definitions *cannot* be applied for responses and , since the occurrence of overshoots, whereas for all other point voltages , those definitions are applicable.(ii)Secondly, calculate the coefficients , , , , , and , so as to determine the parameters , , , and of the normalized transfer functions and obtained from (26) according to the relations
Calculation of coefficients ,, , , , and in (26) might be a tedious task, especially when is large, since these coefficients are produced from (25) as cumbersome expressions which cannot be put in the closed form. So, we must resort to making of a numerical application (say in MATHCAD) for automatic calculation of , , , , , , , , , , and Elmore’s times, for any given set of input parameters , provided that the condition is satisfied.(iii)Calculate Elmore’s delay time () and rise time () of any point step-voltage response having no overshoot, according to definitions in Appendix B and by using (27)
For *RLC* ladder having , [mH], [mS], [F]—excited at by step emf with amplitude [V], the obtained results are summarized in Table 1.

Another interesting ladder in Figure 1 is the one with , , , and . Again, let it be . By using of (8) and Properties 2 and 3, the *point voltage transmittances * and are obtained as follows:

In this case, Elmore’s delay and rise times can be calculated in the similar way as it has been done in (25). The specified set of parameters provided that the voltages of selected ladder points and/or nodes satisfy the condition , Elmore’s times can be calculated by using (26)–(29), but further consideration of this point will be left to the reader.

Also, an interesting ladder is the one with (Figure 1), which resembles to a delay line [13], but it does not truly behave like it and rather may be used for generation of delayed time markers with Elmore’s times expressible in the closed form. To see this, let us produce the *point voltage transmittances * and the *node voltage transmittances * , by using (8), (9), and Property 2 or Case A (10):
Observe that if , then also , and from (30) and (31) it follows that and . This is in obvious physical agreement with the network behaviour in DC operating regime. The previous conclusions could be, also, formally verified by using Remark 1 (Appendix A) in calculation of and for . If excitation of the network with zero initial conditions is step voltage at with amplitude , then . From (30), (31), and Remark 1 we can, also, easily see that and . In this case it can be shown that (i) the node and the point voltages are strictly monotone in [11], so that Elmore’s definitions can be applied leading to (ii) *closed-form* expressions of delay and rise times for *node voltages* [15]. To illustrate the point (i) let us consider the network in Figure 4 whereon capacitance voltages are denoted with . Let us introduce notation , , , (“T”-operation of matrix transposition), and . For the ladder in Figure 4 the following system of state-space equations can be written in -domain:
( column vector), [V] ( column vector of state initial conditions).

Since the real symmetric regular tridiagonal matrix **A** is *hyperdominant* [17], then it is also positive definite and both similar and congruent to diagonal matrix [20], where . So, there exists an orthogonal matrix **Q** [20], such that . If we introduce the coordinate transformation , then the vector differential equation in (32) takes on the following *coordinate decoupled *form:
( column vector of the “transformed” state-space initial conditions).

For , the matrices **Q** and **D** with entries rounded up to 3 decimal places are being obtained asNow, if we suppose that the excitation is the step voltage at with amplitude [V], then the unique solution of the vector differential equation (32) is produced in following form:
The point voltages are obtained according to relations , and finally, for , we can produce by using (36) the closed form solutions of point and node voltages (in [V]), as “” and “” functions of normalized (i.e. dimensionless) “time” :