Mathematical Problems in Engineering / 2013 / Article / Tab 1

Research Article

An 8-Bit ROM-Free AES Design for Low-Cost Applications

Table 1

Performance comparison of different 8-bit AES designs.

DesignTech. (um)ModeMax. clock freq. (MHz)Clock cyclesArea (k-gates)Max. throughput (Mbps)Max. throughput/area
(Mbps/k-gates)
Power consumption

Feldhofer et al. [4]
(Syn.)
0.35 Enc only0.19923.6280.0130.003626.9 uW at100 KHz
Kaps and Sunar [7]
(Syn.)
0.13Enc only0.55344.070.120.029523.85 uW at
500 KHz
Kim et al. [1]
(Syn.)
0.25Enc only0.18703.90.0150.00384.85 uW at
100 KHz
Feldhofer and Wolkerstorfer [5]
(chip)
0.35Both80Enc: 1,032 Dec: 1,1653.49.92.914.5 uW at
100 KHz
1.5 V
Good and Benaissa [14]
(chip)
0.13Enc only123565.54.310.7899 uW at
12 MHz
0.8 V
Ours (chip)0.18Enc only801603.56418.365 uW at
80 MHz
1.8 V
Ours (chip)0.18Both601604.44810.993 uW at
60 MHz
1.8 V

Tech.: technology; Syn.: synthesis; Freq.: frequency.

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