An 8-Bit ROM-Free AES Design for Low-Cost Applications

Table 1

Performance comparison of different 8-bit AES designs.

Design	Tech. (um)	Mode	Max. clock freq. (MHz)	Clock cycles	Area (k-gates)	Max. throughput (Mbps)	Max. throughput/area; (Mbps/k-gates)	Power consumption
Feldhofer et al. [4]; (Syn.)	0.35	Enc only	0.1	992	3.628	0.013	0.0036	26.9 uW at100 KHz
Kaps and Sunar [7]; (Syn.)	0.13	Enc only	0.5	534	4.07	0.12	0.0295	23.85 uW at; 500 KHz
Kim et al. [1]; (Syn.)	0.25	Enc only	0.1	870	3.9	0.015	0.0038	4.85 uW at; 100 KHz
Feldhofer and Wolkerstorfer [5]; (chip)	0.35	Both	80	Enc: 1,032 Dec: 1,165	3.4	9.9	2.91	4.5 uW at; 100 KHz; 1.5 V
Good and Benaissa [14]; (chip)	0.13	Enc only	12	356	5.5	4.31	0.78	99 uW at; 12 MHz; 0.8 V
Ours (chip)	0.18	Enc only	80	160	3.5	64	18.3	65 uW at; 80 MHz; 1.8 V
Ours (chip)	0.18	Both	60	160	4.4	48	10.9	93 uW at; 60 MHz; 1.8 V

∗Tech.: technology; Syn.: synthesis; Freq.: frequency.