This paper introduces a new scheme to achieve a dynamic logic gate which can be adjusted flexibly to obtain different logic functions by adjusting specific parameters of a dynamical system. Based on graphical tools and the threshold mechanism, the distribution of different logic gates is studied, and a transformation method between different logics is given. Analyzing the performance of the dynamical system in the presence of noise, we discover that it is resistant to system noise. Moreover, we find some part of the system can be considered as a leaky integrator which has been already widely applied in engineering. Finally, we provide a proof-of-principle hardware implementation of the proposed scheme to illustrate its effectiveness. With the proposed scheme in hand, it is convenient to build the flexible, robust, and general purpose computing devices such as various network coding routers, communication encoders or decoders, and reconfigurable computer chips.

1. Introduction

For years, the construction of integrated circuits has required a vast amount of time and money for combining different logic gates. In 1985, when the first field-programmable gate array (FPGA) was introduced to the world, the era of reusable “field-programming” began which led to a more flexible implementation of integrated circuits. However, the speed of an FPGA reconfigurable scheme is typically slow, since it needs some time for “rewiring” [1].

In 1998, a novel way of configuring dynamic logic gates was introduced by Sinha and Ditto [2]. Based on a threshold mechanism and chaotic maps, they proposed a scheme to construct dynamic computing systems with flexible logic functions. Their method permitted faster switching (typically within only 0.5 clock cycle) between any two kinds of logics. Nowadays, more schemes have been conducted to construct new types of dynamic logic gates, including synchronization of a nonlinear system [3] as well as the interplay of square waves and noise [4]. Recently, piecewise linear systems were also suggested to construct the dynamic logic architecture [5]. The development of dynamic computing has brought about the appearance of commercial chaotic computer [6].

In this work, we propose a scheme to obtain dynamic logic functions by controlling simple dynamical systems. Based on the threshold mechanism, we give a transformation method between different logics and analyze its antinoise and time-delay characteristics. We find that the scheme is robust to system noise. Furthermore, the main part of the system can be designed based on the leaky integrator which has been applied into different research fields, such as in neuronal or cell analysis and filters related to signal processing. Finally, the scheme is proved to be effective by simulation results of a logic gate circuit.

2. A Scheme of Dynamic Logic Gate

We now propose a new method to change the function of a logic gate flexibly by altering only one parameter or two specific parameters. The formula of its implementation is where is the state of system (1), is the input of the logic gate, determines the convergence rate of the system, and is the control parameter to achieve a transformation between different logics.

When system (1) is stable, its state will converge to the constant as follows:

Based on the threshold mechanism introduced by Murali et al. [4], the output of the logic gate can be determined by

To implement the dynamic logics, the most significant step is to set , , and based on some specific applications. A general situation will be discussed in this paper.

3. Explanation and Discussion of the Proposed Scheme

Typically, we consider that a logic gate has two inputs and one output, for example, we suppose that where and are two logic inputs being either 0 or 1, and and are the parameters. has four possible values. The relationship between the inputs and the output is shown in Table 1.

Figure 1(a) shows the situation of , while in Figure 1(b), and do not have to have any relationships. We can see that both Figures 1(a) and 1(b) can be divided into four logical areas based on the intersections among these four curves, which states that there are four possible ranges for the threshold . Similarly, it can be easily concluded that when or , possible logic functions can be uniformly distributed along the -axis. Hence, when or , the logic values are clearly determined, and a confusion is less likely to occurr. To simplify the problem and avoid some confusion, will be used in this paper. Then, the value of is simply .

Figures 1(c)-1(d) show the judging method for the system output, where the logic value of the system is determined by a curve intersection method, for example, different points in these figures show different states of the system, and the functionality of the system can be altered by changing . For each case of these four possible ranges of , when is known, the logic value can be determined. For example, when , for and , which are shown in Figures 1(c)-1(d), respectively. There are four intersection points between the straight line of and these four curves. In Figure 1(c), since the values of point A and point B are higher than that of , we get by (3); similarly, since the values of point C and point D are lower than that of , we get . Hence, for inputs and , the output is ; while for inputs and , the output is . The corresponding logic gate is an XNOR gate. Similarly, for Figure 1(d), the output for input is and that for inputs , , and , is . That is, the function of AND gate is achieved. It is worth noting that the transformation from XNOR gate to AND can be realized by only changing the control parameter .

By a similar analytical method, all the logic gates can be achieved by the proposed scheme as summarized in Table 2. It is clearly seen that, by only altering the value of , eight types of logic gates can be achieved. For example, when , the possible logic functions that can be achieved are , OR, , , XNOR, , , NAND.

3.1. Analysis in the Presence of Noise

In reality, noise is unavoidable. Generally, there are two types of noise: input noise and system noise. Figure 2(a) shows the output results of system without noise. When the system is added with input noise, then , and its steady state is where is the additive white Gaussian noise (AWGN) and is its intensity. Figures 2(b)-2(c) show the simulation results in the presence of input noise, where (b) the noise range is ?V and (c) the noise range is ?V. It can be clearly seen that when the input noise increases, the system becomes more fluctuating.

When the system is added with system noise, then , and the steady state of the system is

Figures 2(d)-2(e) show the simulation results in the presence of system noise, where (d) the noise range is ?V and(e) the noise range is ?V. We can see from Figures 2(d)-2(e) that the system is strongly resistant to system noise which is one of its most important advantage. Therefore, if we want to build a robust logic gate, then we should put the best effort to minimize the input noise.

3.2. Analysis of Delay

The parameter has an important influence on the response time of the system. The system equation can be rearranged into Hence, we can obtain a system of a leaky integrator whose block diagram is shown in Figure 3. It was proposed as a vital digital signal processing filter which has been very popular in different areas. It has been used to investigate biological and artificial learning processes. Moreover, its famous application in neuron network has made the computation much easier and more powerful [7]. The system here is applicable to study further details in timing and delays.

Note that is the time constant of the system. Then, we get from (7) If is defined as a constant (e.g., ), then the relationship between and is Figure 4 shows the evolution of as . We can see from Figure 4 that the larger the value of is, the shorter the time lag to reach a constant result is, or the more accurate the desired output is. If is very small, the system may not fully response to an input and cannot reach a stable state before the next input starts. This indicates that the response time of each transformation will be longer than the output intervals, and errors will occurr. Therefore, we can say that larger means a faster response time and a more accurate output. However, it is not the larger the better. In practice, larger also means higher energy-consuming amplifier. Users should design a system based on specific applications to make the system work more effectively.

3.3. Circuit Implementation

The physical implementation of a logic cell is an important step for successful applications [8, 9]. Figure 5 shows the equivalent circuit of system (1) by simulation with multisim software.

In Figure 5, there are two parts which are the computation part and the judgment one serving for computing the solution of system (1) as well as judging whether the solution exceeds the threshold, respectively. The left part of Figure 5 corresponds to the computation part in which there are two subtractors, one multiplexer, one amplifier, and one integrator. The right part of Figure 5 corresponds to the judgment one in which there is an operational amplifier serving as the voltage comparator. For subtractor 1, the output is and, for subtractor 2, the output is . For the voltage comparator, we can change the threshold by altering the value of the DC source.

By (1) and (3), all the parameters in the circuit of Figure 5 can be calculated. Therefore, certain circuits can be designed according to specific applications. For example, if all the parameters are set properly, then we can achieve an OR logic gate. Figure 6 gives the stream of input signals , and the output for the OR logic gate. The inputs and are square waves with 10?Vp amplitudes and 2?kHz and 4?kHz frequencies, respectively. The voltage values of , , and are shown in Figure 6 with 200?us/Div time base and 5?V/Div scale.

Similar results can be achieved as the frequencies of the inputs increases. When the frequencies of the inputs become large enough, the lag time must be taken into consideration. As discussed above, the increment of leads to smaller lag time and faster convergence. This phenomenon is obvious for larger frequency inputs.

The proposed method can be used to other systems such as fractional oscillators [10, 11], and we may obtain some potential interesting results.

4. Conclusion

To sum up, a scheme to realize a dynamic logic gate is introduced in this paper. Based on the proposed scheme, all available logics and its transformation method are discussed. Besides, the noise and lag characteristics of the system are studied. We find that the system is resistant to system noise and its response time can be easily controlled. Finally, a circuit implementation for an OR logic gate is provided as an example. Other feasible logic gates can be achieved similarly. The scheme is both straightforward and robust which enables a strong flexible hardware implementation with very low cost. This dynamic logic gate can be applied as a universal basic hardware element to build various kinds of communication encoders and decoders, network coding routers, specific reconfigurable computer chips, graphics processor units, reconfigurable multimedia video cards, or specific systems that require frequent transformations between different logics. Moreover, there are some further significant directions to be investigated such as all kinds of reconfigurable network coding routers and reconfigurable cyclic code encoder or decoder based on the proposed reconfigurable dynamic logic gate. Communication and computer hardware devices based on such dynamic logic scheme may be more flexible and robust than the existing statically wired hardware.


The authors would like to thank the reviewers for their helpful advices. This paper is supported in part by the AoE grant E-02/08 from the University Grants Committee of the Hong Kong Special Administration Region, China, the Hong Kong Scholars Program (Grant no. HJ2012005), the China Postdoctoral Science Foundation Funded Project (Grant no. 2012T50209), the National Natural Science Foundation of China (Grant nos. 61070209, 61100204, 61272402), the Beijing Higher Education Young Elite Teacher Project, the Shenzhen Municipal Key Laboratory of Key Technology and Application (Grant no. C.02.12.00301) and the Fundamental Research Funding of Shenzhen, China (Grant no. C.02.13.00701).