Abstract
A systematic methodology is developed for multi-images encryption and decryption and field programmable gate array (FPGA) embedded implementation by using single discrete time chaotic system. To overcome the traditional limitations that a chaotic system can only encrypt or decrypt one image, this paper initiates a new approach to design n-dimensional (n-D) discrete time chaotic controlled systems via some variables anticontrol, which can achieve multipath drive-response synchronization. To that end, the designed n-dimensional discrete time chaotic controlled systems are used for multi-images encryption and decryption. A generalized design principle and the corresponding implementation steps are also given. Based on the FPGA embedded hardware system working platform with XUP Virtex-II type, a chaotic secure communication system for three digital color images encryption and decryption by using a 7D discrete time chaotic system is designed, and the related system design and hardware implementation results are demonstrated, with the related mathematical problems analyzed.
1. Introduction
Chaos control refers to purposefully eliminating or weakening chaotic behavior of systems through control methods when the chaotic motion is harmful. Since the OGY method was proposed in 1990 [1], much effort has been devoted to the study of controlling chaos. However, not all chaotic behaviors are harmful, and recent research has shown that chaos can actually be useful under certain circumstances, such as liquid mixing, information processing, flexible systems design, and secret communications. Therefore, chaotification by means of making an originally nonchaotic dynamical system chaotic, or enhancing existing chaos, has attracted some special attention lately. In 1994, Schiff et al. proposed the idea of chaos anticontrol [2]. In 1996, Chen and Lai proposed the Chen-Lai algorithm, which uses a linear state feedback controller and a mod-operation for the whole system to make all the Lyapunov exponents of the controlled system strictly positive, thereby obtaining chaos in the sense of Li-Yorke or Devaney [3–7]. Thereafter, Wang and Chen put forward the Wang-Chen algorithm [4, 8]. The idea of the Chen-Lai and Wang-Chen algorithms is to design a linear state feedback controller, which can change the eigenvalues of the system Jacobian matrix, thereby assigning desirable Lyapunov exponents to the controlled system [4]. In addition, some methods are also developed for anticontrol of continuous-time dynamical systems [9–11].
It is well known that the distinct properties of chaos, such as positive Lyapunov exponents, ergodicity, quasirandomness, sensitively dependence on initial conditions, and system parameters, have granted chaotic dynamics as a promising alternative for the conventional cryptographic algorithms. More importantly, unlike the conventional cryptographic algorithms which are mainly based on discrete mathematics, chaos-based cryptography relied on the complex dynamics of nonlinear systems or maps which are deterministic but simple. Therefore, it can provide a fast and secure means for data protection, which is crucial for multimedia data transmission over fast communication channels, such as the broadband internet communication [12–15]. Just because of this, in recent years, numerous efforts have been devoted to develop various chaos-based image encryptions and secure communications. For all that, to the best of our knowledge, it is the most conventional practice that a chaotic system can only encrypt or decrypt one image by means of block cipher-based or stream cipher-based chaos discrete mapping [16–26]. One may ask whether or not there is a possible way further to break such a limitation so as to encrypt and decrypt multi-images by using single chaotic system. This paper gives a positive answer to the question.
In this paper, differing from the Chen-Lai and Wang-Chen algorithms, a new approach for designing n-dimensional discrete-time chaotic systems via some state-variable anticontrol is initiated, and a generalized design principle and the corresponding implementation steps are also given. To be specific, in order to overcome the traditional limitations that a chaotic system can only encrypt or decrypt one image, a discrete time nominal system with a stable saddle-focus at the origin is firstly designed. Then, one can do similarity transformation and introduce a controller on the nominal system via some state variable anticontrol, to obtain the related controlled chaotic system, which can achieve multipath drive-response synchronization. On the basis of this, a systematic methodology can be developed here for multi-images encryption and decryption by using single discrete time chaotic system. To that end, three 160 × 120 BMP digital color images with 24-bit per pixel are taken as examples for implementation and application. On the transmitter side, three 32-bit chaotic stream ciphers generated by a discrete-time chaotic system are used. For every 24-bit pixel, only 8-bit pixel is encrypted each time since the Ethernet transmission protocols and agreements are taken into account. The three encrypted digital color images are transmitted through LAN with only a router by using the time division multiplexing approach. On the receiver end, through a corresponding reverse operation, three encrypted digital color images can be decrypted if synchronization is achieved. Based on the FPGA embedded hardware system working platform with FPGA chip model XUP Virtex-II, a chaotic secure communication system for three digital color images encryption and decryption by using a 7D discrete time chaotic system is designed and implemented, with experimental results demonstrated. Both theoretical analysis and experimental results confirm the feasibility of this approach. More importantly, the main reasons why the presented system works well are given by the rigorous mathematical proof both for chaos existence and rapid synchronized convergence, since both of them play a very important role in image encryption and decryption.
The rest of the paper is organized as follows. A controlled chaotic system is designed via some variable anticontrol in Section 2. A representative example is given in Section 3. Multipath drive-response synchronization based on single chaotic system is given and analyzed in Section 4. FPGA embedded implementation for three digital color images encryption and decryption is implemented and demonstrated in Section 5. The corresponding NIST test results are given in Section 6. Finally, Section 7 concludes the paper.
2. Design of Discrete Time Chaotic System via Some Variable Anticontrol
2.1. Nominal System Design
Consider -dimensional discrete time linear nominal system: where Assume that has a generalized form of block diagonal matrix. In the following, two conditions are involved.
(1) When is an even number, letting , one gets the generalized form of : where is a block matrix, given by
According to (3) with (4), letting , one gets the characteristic roots of at the origin: where .
When , are satisfied, there exist distinct eigenvalues. Particularly, when , characteristic roots of are located inside the unit circle, making the nominal system asymptotically stable.
(2) When is an odd number, letting , one gets the generalized form of : where is a block matrix, also given by (4).
Suppose ; one gets the characteristic roots of at the origin: where .
When , are satisfied, there exist distinct eigenvalues. Especially, when and , characteristic roots of are located inside the unit circle, making the nominal system asymptotically stable.
Do similarity transformation on nominal system (1). It is noted that, except for the block diagonal matrix and , the remaining elements are zeros in . In order to effectively control the nominal system, do similarity transformation on the nominal system (1), such that where is an invertible matrix in the form of
Finally, one gets the nominal system after doing similarity transformation: where
It is especially pointed that, after similarity transformation, and have the same characteristic polynomial and eigenvalues. That is, the nominal system (1) and the converted nominal system (10) have the same stability.
2.2. Controlled Chaotic System Design via Some Variable Anticontrol
According to (10), by selecting from as feedback control variables, one can design a uniformly bounded controller: where is a uniformly bounded nonlinear function, such as periodic or modular functions. Here, select as a modular function . In addition, parameters are controller gain and are controller supremum. is the number of feedback control variables . is the subscript value of the first feedback control variable .
From (10)–(12), one obtains the controlled system, given by The corresponding component form of (13) is given by
Theorem 1. Consider the controlled system (14). If the following two conditions are satisfied, then the controlled system (14) is chaotic.(i)n characteristic roots of are located inside the unit circle, making the corresponding nominal system (10) asymptotically stable.(ii)The controller (12) is uniformly bounded. By selecting parameters and , the controlled system matrix of system (14) has at least one characteristic root located outside the unit circle, where is given by
Proof. In the many features of chaos, two basic characteristics, namely, being globally bounded while having a positive Lyapunov exponent, are widely used as criteria for chaos [4]. Consider the solution of (14):
It follows from conditions (i) and (ii) that, since and , one has
where is a geometric series with common ratio . Hence, one gets
Substituting (18) into (17), one gets
Therefore, is globally bounded.
According to the Lyapunov exponent formula for discrete-time chaotic systems,
where . When has at least one characteristic root located outside the unit circle, system (14) generates at least one positive Lyapunov exponent.
Therefore, the controlled system (14) is chaotic since it is globally bounded and has at least one positive Lyapunov exponent.
3. A Typical Example
Consider a 7D nominal matrix in the form of where , , , , , , and .
Suppose that the similarity transformation is According to , one gets the converted nominal matrix, given by
By selecting three feedback state variables as , , and , the controller is obtained by where parameters , , , and , , .
According to (23) with (24), one gets the controlled system, given by
where is in the form of
By calculating, one gets the seven eigenvalues of and as follows: Therefore, all the characteristic roots of and are located inside the unit circle.
Similarly, one gets seven eigenvalues of as follows: Hence, in the controlled system (25), seven eigenvalues of are located outside the unit circle.
According to Theorem 1, the controlled system (25) is chaotic, with a chaotic attractor as shown in Figure 1.
| (a) plane projection |
| (b) plane projection |
| (c) plane projection |
| (d) plane projection |
| (e) plane projection |
| (f) plane projection |
4. Principle of Multipath Drive-Response Synchronization via Single Chaotic System
In this section, the principle of multipath drive-response synchronization based on single chaotic system is investigated.
4.1. Multipath Drive-Response Synchronization via Single Chaotic System
A diagram for multipath drive-response synchronization via single chaotic system is shown in Figure 2, and its fundamental working principles are described as follows.(i)The state variables generated by the drive system are used for chaotic encryption sequences, which encrypt pixels of images. Therefore, one can obtain the encrypted signals .(ii)The encrypted signals are feedback to the drive system. The related feedback principle is that, except for jth equation, the drive system state variables of the remaining equations are replaced by , where.(iii)The encrypted signals are transmitted through Ethernet by using the time division multiplexing approach, which are used for driving the response system. The related drive principle is that, except for jth equation, the response system state variables of the remaining equations are replaced by , where .
(a) The drive system
(b) The response system
On the transmitter side, according to (14) and Figure 2, the drive system is obtained by Similarly, at the receiver end, the response system is described by
4.2. Relationship of , , and
In (29) and (30), is the number of dimensions of the chaotic system, is the number of feedback control variables , and it is also the number of encrypted and decrypted images. is the subscript value of the first feedback control variable . In order to weigh both the number of encrypted images and the safety performance, is determined by
According to (31), when is determined, one can obtain the subscript value of the first feedback control variable , given by Obviously, inequality holds.
4.3. Analysis of Multipath Drive-Response Chaotic Synchronization
Theorem 2. Consider the drive system (29) and the response system (30). If the following two conditions are satisfied, then the response system can synchronize the drive system.(i)The parameters of (29) and (30) exactly match.(ii)Eigenvalue roots of nominal matrix and satisfy and .
Proof. According to (29), (30), and condition (i) from Theorem 2, one gets the error system, given by
where with , , , with, and and with .
From (33), one gets
By taking norm on both sides of (34), one has
From condition (ii) of Theorem 2, one has . Hence, the error system (35) is asymptotically stable. Therefore,
where .
Furthermore, from condition (ii) of Theorem 2, hold, such that
Substituting (36) into (37), one has
where .
By combining (36) with (38), one has
where .
From (39), it is concluded that the drive system (29) and the response system (30) can synchronize. Nevertheless, it should be noted that, in practical situations, only a few iterative steps are needed for synchronization.
4.4. A 7D Three-Path Drive-Response Synchronization System
According to Figure 2 and (29)-(30), let . From (31)-(32), one gets and . A diagram for 7D three-path drive-response synchronization system is shown in Figure 3.
From Figure 3, the 7D drive system is obtained by Similarly, the response system is described by where the controller is determined by (24), parameters are given by (23), and , are
According to (40) and (41), if all parameters exactly match, the synchronization simulation results are shown in Figure 4, from which one can see that the synchronization can be achieved only about 10 iterative steps needed. The receiver can decrypt three-path encrypted signals through synchronization, given by
5. FPGA Embedded Implementation for Three Images Encryption and Decryption
In this section, a chaotic secure communication system for three digital color images encryption and decryption by using a 7D discrete time chaotic system is designed, based on FPGA embedded hardware system working platform with XUP Virtex-II type. The corresponding system design and hardware implementation results are then demonstrated. Furthermore, parameters safety performance test results are also given.
5.1. Hardware and Software Systems Design
FPGA embedded hardware system working platform with XUP Virtex-II type consists of three parts: an encrypter, a decryptor, and the Ethernet, as shown in Figure 5. Hardware design result of FPGA embedded system on chip is shown in Figure 6, which consists of twelve parts: two processor cores (ppc405_0 and ppc405_1); a processor local bus (PLB); an on-chip peripheral bus (OPB); a PLB to OPB bridge (plb2opb); a DDR synchronous dynamic random access memory mounted on PLB (plb_ddr); an OPB to device control register bus bridge (opb2dcr); a joint test action group (JTAG); a clock IP (clk_IP); a controller mounted on OPB (opb_controller); a block RAM mounted on PLB (plb_bram); a video graphics array frame buffer (VGA frame buffer); 57 input and output pins (Pin). Software system design consists of four parts: encryption algorithms, decryption algorithms, udp protocol, and six images display simultaneously, with their design flowcharts as shown in Figures 7, 8, 9, and 10, respectively.
In our hardware experiments, three 160 × 120 BMP digital color images with 24-bit per pixel are taken as typical examples. On the transmitter side, three 32-bit chaotic stream ciphers , , and generated by 7D discrete-time chaotic system (29) are used for encrypting three 24-bit pixels , , and of the corresponding three digital color images simultaneously. For every 24-bit pixel, only 8-bit pixel is encrypted each time since the Ethernet transmission protocols and agreements are taken into account. Therefore, encrypting three 160 × 120 BMP digital color images with 24-bit per pixel needs to iterate 160 × 120 × 3 times. The three encrypted digital color images are transmitted through Ethernet by using the time division multiplexing approach. At the receiver end, three 32-bit chaotic stream ciphers , , and generated by 7D discrete-time chaotic system (30) are used for the corresponding decrypting operation. When chaotic synchronization between the drive system (29) and the response system (30) is achieved, three encrypted digital color images can be decrypted.
5.2. Hardware Implementation Results
FPGA embedded hardware implementation results are shown in Figures 11, 12, 13, and 14. Among 7D chaotic attractors which are in agreement with simulation results given by Figures 1(a)–1(f), three original and encrypted images on the transmitter side (from top to bottom), three received encrypted and decrypted images at the receiver end (from top to bottom) are shown in Figures 11–13, all generated by FPGA. When all the parameters match exactly, the receiver can decrypt three original digital color images through synchronization, as shown in Figure 13. But the receiver cannot decrypt three original digital color images if the mismatched error of one parameter between the sender and the receiver reaches magnitude of , even though other parameters match exactly, as shown in Figure 14.
6. NIST Safety Performance Test Results
In our NIST safety performance test for three images encryption and decryption systems (40) with (41), 10 sequences ( = 10) of 1,000,0000 bits are generated and tested. If the value of any test is smaller than 0.0001, the sequences are considered to be not good enough and the generator is unsuitable. Table 1 shows value of sequences , , and based on discrete chaotic iterations using scheme. If there are at least two statistical values in a test, this test is marked with an asterisk and the average value is computed to characterize the statistics. We can see in Table 1 that the sequences have successfully passed the NIST statistical test suite.
7. Conclusions
In order to break the traditional limitations that a chaotic system can only encrypt or decrypt one image, this paper has developed a systematic methodology for multi-images encryption and decryption by using single discrete time chaotic system. A generalized design principle and the corresponding implementation steps are also given. Based on the FPGA embedded hardware system working platform with XUP Virtex-II type, a chaotic secure communication system for three digital color images encryption and decryption by using a 7D discrete time chaotic system is designed and implemented, with hardware experiments and NIST safety performance tests demonstrated. Both theoretical analysis and experimental results confirm the feasibility of this approach.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
Acknowledgments
This work was supported by the National Natural Science Foundation of China under Grant 61172023 and by the Specialized Research Foundation of Doctoral Subjects of Chinese Education Ministry under Grant 20114420110003.