Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

Table 1

Partitioning optimization of GA compared with hybrid algorithm.

Circuit	GA			Hybrid
	Delay (ps)	𝑇 (s)	Best (s)	Delay (ps)	𝑇 (s)	Best (s)
S1196	396	375	373	301	184	134
S1238	475	397	365	408	187	160
S1494	614	1228	1040	585	616	427
S2091	302	94	32	225	616	16
S3330	571	2096	2074	533	470	994
S5378	587	2687	2686	590	1078	1100