Research Article  Open Access
Xin Gao, HouJun Wang, Zhen Liu, "Handling Fault Diagnosis Problem of LinearAnalogue Circuits with Voltage Phasor Measurement", Mathematical Problems in Engineering, vol. 2014, Article ID 879402, 13 pages, 2014. https://doi.org/10.1155/2014/879402
Handling Fault Diagnosis Problem of LinearAnalogue Circuits with Voltage Phasor Measurement
Abstract
This paper proposes a novel method to estimate the influence of hardfault in linearanalogue circuit system based on the measurement of voltage phasor with assistant branch introduced. Furthermore, a new fault diagnosis strategy based on the voltage phasor modeling is established, and the tolerance influence on the corresponding voltage measurement is also discussed. The actual analogue circuit test shows us that the proposed method is effective and reliable to locate the accurate fault signature in voltage measurement for the fault diagnosis. As a matter of fact, it includes both the amplitude and phase information in a complex value form when the linearanalogue circuit is under the AC test. Besides, it can be also applied to ambiguous groups and the sensitive testfrequencies determination in the process of fault diagnosis,while the effectiveness of multifrequencies test has also been testified through testfrequencies sweeping investigation and the maximum error evaluation of fault component value in the second circuit example.
1. Introduction
The fault diagnosis problem has been one of the most critical issues in the test of largescale industrial or military digitalanalogue hybrid circuit. Furthermore, according to statistics, in the mixedsignal (circuit) system, more than faults occur in the analogue section [1], and the corresponding test cost accounts for of the total test cost and 30%–50% of manufacturing cost, as well as the test time which is more than of the total test time [2]. Therefore, there still exists a pressing need to locate an effective and simple method handling fault diagnosis in the analogue circuits.
Up to now, there have been extensive researches on analogue circuit fault diagnosis, in which scientists developed various fault diagnosis methods through different excitation for the circuit test: (a) DC test: it is the simplest and fastest one; however, it might fail because of energystorage components; (b) AC test [3–5]: it uses a periodic signal as external stimulus for the circuit under test (CUT) and overcomes the shortcomings of DC test, as well as requiring relatively simple test; (c) aperiodic signals stimulus test [6–9]: it owns the most abundant features about circuit state but needs most complex test requirement.
To compromise the test simplicity (e.g., less time or money consumption) and the test effectiveness (e.g., higher fault detection and/or isolation rate), one can recommend the AC test in this paper. Moreover, depending on the number of frequency components in a stimulus, AC tests are further classified into two categories: singletone and multitone test. In practice, multitone test stimuli can be composed of signals of different frequencies; therefore, in this paper, all concerns should be on the singletone test: sinusoid signal test.
Eventually, this paper proposes a robust voltage phasorbased method for the circuit diagnosis, when the sinusoid signal stimulus is used in analogue circuit such that this method is robust, because of the fault modeling being established according to the rigorous theories. What is more, there are at least 3 more advantages: (a) the corresponding fault signature (voltage measurement) is simple to calculate in the process of circuit diagnosis, compared to the feature used in [10, 11]; (b) the fault diagnosis can be found in toleration circumstance to benefit us in the actual fault diagnosis with given requirement (e.g., the fault detection and/or isolation rate); (c) although the voltage measurement is discussed in a form of complex value for a AC test, it actually can be generalized to the case of real voltage measurement in the DC test.
In the end of this section, all of critical aspects of fault diagnosis discussed in this paper are listed as follows: (a) the calculation of voltage phasor value for a faulty linearanalogue circuit with a given AC test, (b) the influence of component tolerance on circuit voltage phasor response, (c) the AC test selection for fault diagnosis based on voltage phasor measurement, and (d) the further discussion about ambiguous groups determination and evaluation of multifrequencies test.
The rest of paper is organized as follows. At first, Section 2 establishes the theoretical basis for all the discussed contents as mentioned above. Then Section 3 tests the effectiveness of theories of Section 2 in some representative linear circuits. In Section 4, considering an important aspect—ambiguity groups determination was often discussed in linearanalogue circuit diagnosis in the past; one also discusses this topic on the basis of proposed fault modeling in this paper. Besides, the effectiveness of multifrequencies test in the second circuit example is further evaluated. In the end, the corresponding conclusions and prospects are made in Section 5.
2. Basic Principle
2.1. Voltage Phasor Modeling in Fault Diagnosis
Without loss of generality, one assumes that a linearanalogue circuit in Figure 1 is excited by an independent voltage stimuli as shown in (1). Besides, this signal is expressed in a phasor form of (2), according to the linear circuit theory in [12]: where is the amplitude of sinusoidal signal of , is a known fixed frequency, and represents the phase of this signal. Therefore, voltage phasor is a complex value including the information of amplitude and phase from the stimuli of
With the input signal , the circuit output response is also a sinusoidal signal , whose voltage phasor form is . Then, on the basis of the superposition theorem [13, 14], one can establish (3) for the voltage phasor at testnode as follows: where is the complex transmission factor between and , while is the complex transmission factor from to .
As a matter of fact, the value of equals the value of voltage phasor response at , if the input stimulus is the sole incentive and component is in shortcircuit state. In order to be convenient speaking in this paper, one can set it as .
Ulteriorly, on the basis of Thevenin’s theorem in the linearanalogue circuit, one can get the following: where the () represents a voltage phasor through the circuit branch , when component is in normal (open) state. Besides, is a complex impedance for component . Meanwhile, is Thevenin’s equivalent impedance seeing through the circuit ports and , when component is open.
Due to the formula and (3)(4), this paper finds the following:
In particular, one assumes that component is in opencircuit state; then the voltage phasor at is as follows:
At last, in accordance with (5) and (6), there exists a formula as follows:
In other words, (8) is formulated as follows: where represents an invariable continuous function for a given linearanalogue circuit.
In the case of parametric fault of , the value of or is considered as constant. At last, “Theorem 1” can be found.
Theorem 1. In analogue circuit of Figure 1, the potential faulty component owns the nominal impedance value , and the nominal response is ; then the faulty response caused by parametric fault of at testnode can be calculated according to the following equation: where the value of is a constant determined by .
Proof. With the statement in (8), it is obvious to find following equations:
Later, if (10) is divided by (11), will be eliminated. Then Theorem 1 is obtained.
Theorem 1 builds up the accurate analytic expression of fault response, because of parametric fault of component . It also tells us that based on the voltage phasor measurement or estimation in a few fault states (e.g., opencircuit state, shortcircuit state, and nominal state), one can induce all the fault responses for any continuous parametric faults.
In particular, if component is resistance or capacitance , which means or , “Theorem 2” is given as follows.
Theorem 2. The faulty response curve of voltage phasor in Figure 1 can be determined by (14)(15), respectively, if the fault component is capacitance or resistance in linearanalogue circuit.
Proof. Without loss of generality, let , , , and , then (12) is given as follows:
where .
Furthermore, the results of (12) lead to (13), when component is capacitance (, ) or resistance (, ) as follows:
where , , , and .
It is obvious to find that . Then if one sets and , (14)(15) can be found as follows: where , ,, , , and .
2.2. Voltage Phasor Measurement and Estimation
In the Theorems 1 and 2, we know that by separately measuring voltage phasor in the nominal circuit state and () in open (short)circuit state, one can calculate the value of the output voltage phasor in all parametric fault states, which benefit us to accomplish the circuit fault modeling.
However, the opencircuit and shortcircuit faults are the most catastrophic fault states, which means the corresponding analogue circuit in these states has to be destroyed in both physical structure and circuit function; that is, one can not drive the actual circuit into these two dangerous states for constructing the fault modeling. Therefore, there are 2 possible means to solve this tricky thing: faulty responses are simulated in PSpicemodeled circuit, which has been utilized in the SBT method; faulty responses can also be estimated through the voltage phasor measurement and calculation as shown in this section.
In Figure 2(a), when the circuit is in nominal state, one can set stimulus and measure the voltage phasor through component ’s branch as well as locate the value of . Furthermore, in Figure 2(b), by adding an auxiliary stimulus with voltage phasor stimuli representation of in Figure 2(b), in this case, the voltage phasor at will be , while the value of turns to . After this, Lemma 3 is acquired.
(a)
(b)
(c)
(d)
Lemma 3. The faulty response , which is caused by shortcircuit fault of component , is as follows:
Proof. According to the superposition theorem in linear circuit theories and (3), . Furthermore, the value of is the CUT output at when the original input stimulus is shortened but the auxiliary stimulus is preserved; that is, . As a result, Lemma 3 is founded.
Lemma 3 means that, with the measurement of voltage phasor in Figures 2(b) and 2(d), one can estimate the shortcircuit response at before the potential faulty component is involved in shortcircuit fault state. The cost is the input stimulus should be shortened in the process of voltage measurement. In order not to shorten any stimulus or port for the estimation of , Theorem 4 is established.
Theorem 4. The faulty response , which is caused by shortcircuit fault of component , is as follows:
Proof. According to the process of deduction of Lemma 3, it is apparent to know that . By substituting it to (6), one obtains the following equations:
Furthermore, when circuit is in normal state, the complex impedance of is , and then there is the following equation:
Based on (6) and (18)(19), one further knows the following equation:
In general case, ; that is, . Hence, with , one can get the solution of Theorem 2.
According to Theorems 1 and 2, if one can further obtain the value of , the fault modeling with voltage phasor will be established. In fact, the faulty response of can be calculated with Theorem 5.
Theorem 5. If one replaces the auxiliary stimulus in Figure 2(b) with an auxiliary branch owning impedance , then the output response . Thus, the value of faulty response at , which is caused by opencircuit fault of component , is estimated through (21). Here, as follows:
Proof. Assume that the faulty complex impedance of is , while the nominal complex impedance of is ; then according to (10)(11), (22) is as follows:
According to (22), there should be (23), in which , and :
At last, Theorem 5 is established by the result of (23).
In short, the paralleled impedance of achieves the impedance transformation in Theorem 5; then the hardfault state (opencircuit) influence can be estimated with the help of auxiliary branch and other circuit responses (e.g., , ).
2.3. Tolerance Influence on the Voltage Phasor
According to (9) in Theorem 1, Lemma 6 is found.
Lemma 6. Set the faulty value of component to , and the corresponding circuit output voltage phasor at is ; then within the tolerance circumstance, there are 2 continuous functions shown as follows: where () is obtained, when component is in the opencircuit state (shortcircuit state) with all other faultfree components according to component tolerance. And the value of is measured in the case that all components are set around the nominal component values within the tolerance range.
Proof. According to (9), one can assure that there are 2 equations without consideration of tolerance: where . Therefore, Lemma 6 is correct while taking the account of tolerance influence in the analogue circuit.
On the basis of Lemma 6 and the basic principle of continuous function, one can conclude that if the faulty value of component varies continuously in a given parametric range as shown in (26), the corresponding value of voltage phasor at the circuit output should be bounded in (27) as follows:
Without loss of generality, if the potential faulty component is resistance , whose nominal value is and the component tolerance is , then the component value variation within tolerance range is . Furthermore, the maximum range of component parameters is , . Then Lemma 7 and Theorem 8 can be listed.
Lemma 7. Assume that component owns the following parametric values: (a) and (b) , and these values satisfy: ; ; then the conclusions are made in (28) as follows: where the potential faulty component owns the parametric range of , , when the corresponding voltage phasor value is . And is the voltage phasor corresponding to the maximum range of component parameters being , .
Proof. If component can take these values: and , which means and , then = .
Therefore, if the value of component varies within parametric range of , according to the continuous function in (24), Lemma 7 is established.
Theorem 8. The accurate parametric range of is , which can be determined according to (29), when the faulty component value is or . Consider where and are shown in Lemma 7, and , which has been given in Lemma 6.
Lemma 7 and Theorem 8 tell us that in toleranceinfluencing circuit, if the potential faulty component is in a continuous faulty parametric range, the corresponding variation range of faulty response at can be estimated through the simulation or measurement of voltage phasor in some particular discrete faulty parameter cases. Or in other words, the limited simulations or measurements in practice could bring us accurate faulty response range estimation.
Furthermore, in the simulation or measurement of voltage phasor in discrete faulty parameter cases, Lemma 9 is shown.
Lemma 9. As for a general linearanalogue circuit, it can be considered as a network with branches and nodes (one of the nodes is reference node, e.g., ground). Let be the branch complex admittance matrix, represent the voltage phasor measurement vector, and be a complex current vector, then it is obvious to find (30) as follows:
The tolerance and discrete fault values influencing the corresponding branches (components) introduce these increment matrices: , , and as follows:
Without loss of generality, assume that the excitation current is fixed; then . As a result, Theorem 10 is established.
Theorem 10. Given a discrete faulty parameter for component through its branch, the corresponding voltage phasor (real part and image part) follows normal distribution in the toleranceinfluencing circuit, if (a) the elements in the matrix for all faultfree components follow the normal distribution; (b) .
Proof. Due to the solution of (30)(31) and , one can get
Therefore, each element of can be linearly expressed by the elements in matrix . And the corresponding voltage phasor (real part and image part) follows normal distribution if the elements in the matrix follow the normal distribution.
Theorem 10 states that the complex parametric faults (discrete fault values) lead to the faulty responses at , whose real part and image part number should conform to the normal distribution.
2.4. Fault Diagnosis in LinearAnalogue Circuit
In a linearanalogue circuit under test (CUT), the estimated range of voltage phasor is represented in Table 1. Here, the fault states set is , . And is the number of fault states in linearanalogue circuit. Each fault state can represent one of following continuous fault parameter ranges: (a) or for th component branch in the circuit, where and the tolerance is and (b) for th component in the circuit, where the component tolerance () exerts on all other faultfree elements in the circuit and is the representative discrete fault value as the central value of parametric range.
Considering the voltage phasor is dependent on the input stimulus at testnode , which could variate with different testfrequency of signal; thus, the testfrequency set can be shown in the columns of Table 1: , for the best fault diagnosis.
The corresponding voltage phasor value range in the rows of Table 1 can be separated into two parts: one is from the real part of voltage phasor value (e.g., [], ), while the other is from the image part of voltage phasor value (e.g., [], ). Therefore, based on the corresponding values in Table 1, the fault diagnosis for a set of parametric faults is categorized into fault detection and isolation: (a) a fault can be detected if the corresponding value of voltage phasor range owns no parametric overlaps with the faultfree state. (b) Meanwhile, a fault can be isolated meaning that this fault state can be distinguished from all other fault states because of no intersection of complex voltages range.
To be convenient speaking in the following sections, one sets the representation of and ; then following functions are shown in (33)(34) as follows: where . where .
Then the result of fault diagnosis is measured through fault detection rate (FDR) and fault isolation rate (FIR) as follows:Fault detection rate (FDR): the ratio of fault states that can be detected in a given fault states set as follows: where .Fault isolation rate (FIR): the ratio of fault states pair can be isolated based on a given fault states pair set as follows: where .
3. Computational Example
In this section, there are 2 representative examples to validate the proposed fault diagnosis based on the voltage phasor analysis in both tolerancefree and toleranceinfluencing circuit. To be simplifying the question, in the first example of this section, the proposed method to estimate the parametric fault response and hardfaults influence is concerned with the theories from Theorem 1 and Theorems 4–8 and their corresponding lemmas. After this, in the second example, one can organize the complex voltages as what has been shown in Table 1 and select appropriate testsignal frequencies; that is, we can use these selected columns for fault diagnosis of a given fault states set, in order to satisfy the requirement of and .
3.1. Thomas Filter Example
The first example circuit is shown in Figure 3, while the circuit output is at . This example is used to demonstrate the critical results of proposed method for fault diagnosis based on complex voltages estimation, and the parametric faults are as follows: (a) discrete fault values in tolerancefree case as shown in Tables 2 and 4; (b) the parameter of faulty components varies from to of its discrete fault values in Table 5. Here, the former one is to testify the accuracy of Theorems 1, 4, and 5, while the latter one is used to demonstrate the process of faulty response estimation with consideration of tolerance and continuous parametric fault pattern diagnosis in the linearanalogue circuit.

In addition, in this circuit example, the stimulus signal (green sketch in Figure 4) is as follows: (a) the amplitude is (V); (b) the testfrequency is set as 1.5 kHz; (c) the phase of this signal is zero. Furthermore, the circuit response in nominal circuit state is also given in Figure 4 (red sketch), which satisfies: (a) the amplitude is (V); (b) the testfrequency is set as 1.5 kHz; (c) the phase of this signal is . Therefore, according to the relationship between (1) and (2), the corresponding phasor is (V) ( (V)).
In order to estimate the faulty responses because of parametric faults in second column of Table 2, one should primarily estimate all hardfaults influence in this circuit. For instance, as for testnode , if is assumed to be the potential parametric fault component, the corresponding circuit output voltage phasor at testnode could be estimated as the following procedure in the circuit with nominal parametric values: (a) the circuit is in nominal state (faultfree), and the stimulus is (V); (b) the voltage phasor through branch is (V), and one can locate this complex value through the amplitude and phase of sinusoidal signal at testnode ; (c) as shown in Figure 3, one adds an auxiliary voltage stimulus (V), and at the same time, the voltage phasor at testnode is (V); (d) let all these measurements be in (17), the solution of (17) is (V).
The similar measurements and calculations are processed for the other hardfaults influence estimations at testnode ; after that, the corresponding voltage phasor values are shown in Table 3.
