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Mathematical Problems in Engineering
Volume 2015 (2015), Article ID 174289, 24 pages
http://dx.doi.org/10.1155/2015/174289
Research Article

Maximum Likelihood Estimation of Clock Skew in IEEE 1588 with Fractional Gaussian Noise

Department of Electrical and Electronic Engineering, Ariel University, Ariel 40700, Israel

Received 19 October 2014; Revised 6 February 2015; Accepted 23 February 2015

Academic Editor: Frédéric Hamelin

Copyright © 2015 Chagai Levy and Monika Pinchas. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

To support system-wide synchronization accuracy and precision in the sub-microsecond range without using GPS technique, the precise time protocol (PTP) standard IEEE-1588 v2 is chosen. Recently, a new clock skew estimation technique was proposed for the slave based on a dual slave clock method that assumes that the packet delay variation (PDV) in the Ethernet network is a constant delay. However, papers dealing with the Ethernet network have shown that this PDV is a long range dependency (LRD) process which may be modeled as a fractional Gaussian noise (fGn) with Hurst exponent () in the range of . In this paper, we propose a new clock skew estimator based on the maximum likelihood (ML) technique and derive an approximated expression for the Cramer-Rao lower bound (CRLB) both valid for the case where the PDV is modeled as fGn (). Simulation results indicate that our new clock skew method outperforms the dual slave clock approach and that the simulated mean square error (MSE) obtained by our new proposed clock skew estimator approaches asymptotically the developed CRLB.