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Mathematical Problems in Engineering
Volume 2015 (2015), Article ID 410172, 13 pages
http://dx.doi.org/10.1155/2015/410172
Research Article

A Probabilistic Spatial Distribution Model for Wire Faults in Parallel Network-on-Chip Links

Faculty of Engineering and Technology, Cyprus University of Technology, 3603 Limassol, Cyprus

Received 4 October 2014; Accepted 11 January 2015

Academic Editor: Jinhu Lü

Copyright © 2015 Arseniy Vitkovskiy et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. S. R. Vangal, J. Howard, G. Ruhl et al., “An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 29–41, 2008. View at Google Scholar
  2. S. Bell, B. Edwards, J. Amann et al., “TILE64 processor: a 64-core SoC with mesh interconnect,” in Proceedings of the IEEE International Solid State Circuits Conference, pp. 588–598, February 2008. View at Publisher · View at Google Scholar · View at Scopus
  3. T. Bjerregaard and S. Mahadevan, “A survey of research and practices of network-on-chip,” ACM Computing Surveys, vol. 38, no. 1, pp. 71–121, 2006. View at Google Scholar · View at Scopus
  4. R. Marculescu, U. Y. Ogras, L.-S. Peh, N. E. Jerger, and Y. Hoskote, “Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 1, pp. 3–21, 2009. View at Publisher · View at Google Scholar · View at Scopus
  5. J. D. Owens, W. J. Dally, R. Ho, D. N. Jayashima, S. W. Keckler, and L.-S. Peh, “Research challenges for on-chip interconnection networks,” IEEE Micro, vol. 27, no. 5, pp. 96–108, 2007. View at Publisher · View at Google Scholar · View at Scopus
  6. W. J. Dally and B. Towles, “Route packets not wires: on-chip interconnection networks,” in Proceedings of the IEEE Design Automation Conference, pp. 684–689, May 2001.
  7. D. Bertozzi and L. Benini, “Xpipes: a network-on-chip architecture for gigascale systems-on-chip,” IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18–31, 2004. View at Publisher · View at Google Scholar · View at Scopus
  8. J. Duato, S. Yalamanchili, and L. Ni, Interconnection Networks: An Engineering Approach, Morgan Kaufmann, Boston, Mass, USA, 2002.
  9. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2004.
  10. J. Lü, X. Yu, G. Chen, and D. Cheng, “Characterizing the synchronizability of small-world dynamical networks,” IEEE Transactions on Circuits and Systems. I. Regular Papers, vol. 51, no. 4, pp. 787–796, 2004. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  11. J. Zhou, J.-A. Lu, and J. Lü, “Pinning adaptive synchronization of a general complex dynamical network,” Automatica, vol. 44, no. 4, pp. 996–1003, 2008. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  12. J. Lü and G. Chen, “A time-varying complex dynamical network model and its controlled synchronization criteria,” IEEE Transactions on Automatic Control, vol. 50, no. 6, pp. 841–846, 2005. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  13. ITRS International Technology Roadmap for Semiconductors, Process Integration, Devices, and Structures (PIDS), 2009.
  14. A. Morgenshtein, I. Cidon, A. Kolodny, and R. Ginosar, “Comparative analysis of serial vs parallel links in NOC,” in Proceedings of the International Symposium on System-on-Chip, pp. 185–188, November 2004. View at Scopus
  15. K. Constantinides, S. Plaza, J. Blome et al., “BulletProof: a defect-tolerant CMP switch architecture,” in Proceedings of the International Symposium on High-Performance Computer Architecture, pp. 5–16, February 2006.
  16. S. Borkar, “Designing reliable systems from unreliable components: the challenges of transistor variability and degradation,” IEEE Micro, vol. 25, no. 6, pp. 10–16, 2005. View at Publisher · View at Google Scholar · View at Scopus
  17. G. de Micheli and L. Benini, Networks on Chips: Technology and Tools (Systems on Silicon), Morgan Kaufmann, Boston, Mass, USA, 2006.
  18. T. Lehtonen, D. Wolpert, P. Liljeberg, J. Plosila, and P. Ampadu, “Self-adaptive system for addressing permanent errors in on-chip interconnects,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 4, pp. 527–540, 2010. View at Publisher · View at Google Scholar · View at Scopus
  19. S. R. Nassif, N. Mehta, and C. Yu, “A resilience roadmap,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '10), pp. 1011–1016, March 2010. View at Scopus
  20. J. Duato, “A theory of fault-tolerant routing in wormhole networks,” IEEE Transactions on Parallel and Distributed Systems, vol. 8, no. 8, pp. 790–802, 1997. View at Publisher · View at Google Scholar · View at Scopus
  21. M. Radetzki, C. Feng, X. Zhao, and A. Jantsch, “Methods for fault tolerance in networks-on-chip,” ACM Computing Surveys, vol. 46, no. 1, article 8, 2013. View at Publisher · View at Google Scholar · View at Scopus
  22. T. Bjerregaard and S. Mahadevan, “A survey of research and practices of network-on-chip,” ACM Computing Surveys, vol. 38, no. 1, article 51, 2006. View at Publisher · View at Google Scholar
  23. A. Vitkovskiy, V. Soteriou, and C. Nicopoulos, “A fine-grained link-level fault-tolerant mechanism for networks-on-chip,” in Proceedings of the 28th IEEE International Conference on Computer Design (ICCD '10), pp. 447–454, Amsterdam, The Netherlands, October 2010. View at Publisher · View at Google Scholar · View at Scopus
  24. A. Vitkovskiy, V. Soteriou, and C. Nicopoulos, “A dynamically adjusting gracefully degrading link-level fault-tolerant mechanism for NoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 8, pp. 1235–1248, 2012. View at Publisher · View at Google Scholar · View at Scopus
  25. M. Palesi, S. Kumar, and V. Catania, “Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 3, pp. 426–440, 2010. View at Publisher · View at Google Scholar · View at Scopus
  26. A. Vitkovskiy, P. Christodoulides, and V. Soteriou, “A combinatorial application of necklaces: modeling individual link failures in parallel network-on-chip interconnect links,” in Proceedings of the World Congress on Engineering, London, UK, July 2012, Lecture Notes in Engineering and Computer Science, pp. 125–130, Cyprus University of Technology, 2012. View at Google Scholar
  27. R. C. Lyndon, “On Burnside's problem,” Transactions of the American Mathematical Society, vol. 77, pp. 202–215, 1954. View at Google Scholar · View at MathSciNet
  28. L. Pebody, “Reconstructing odd necklaces,” Combinatorics, Probability and Computing, vol. 16, no. 4, pp. 503–514, 2007. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  29. N. Alon, “Splitting necklaces,” Advances in Mathematics, vol. 63, no. 3, pp. 247–253, 1987. View at Publisher · View at Google Scholar · View at MathSciNet · View at Scopus
  30. S. W. Golomb, “Combinatorial proof of Fermat’s ‘little’ theorem,” The American Mathematical Monthly, vol. 63, no. 10, p. 718, 1956. View at Publisher · View at Google Scholar · View at MathSciNet
  31. P. Erdos and A. Renyi, “On random graphs,” Publicationes Mathematicae Debrecen, vol. 6, pp. 290–297, 1959. View at Google Scholar
  32. M. E. J. Newman, “Random graphs as models of networks,” in Handbook of Graphs and Networks, S. Bornholdt and H. G. Schuster, Eds., pp. 35–68, Wiley-VCH, Berlin, Germany, 2003. View at Google Scholar · View at MathSciNet
  33. E. W. Weisstein, “Necklace,” MathWorld—A Wolfram Web Resource, http://mathworld.wolfram.com/Necklace.html.
  34. D. E. Knuth, The Art of Computer Programming: Vol. 4: A Combinatorial Algorithms, Part 1, Addison-Wesley, Upper Saddle River, NJ, USA, 2011.
  35. The Object Server, “Necklaces, Unlabelled Necklaces, Lyndon Words, De Bruijn Sequences,” http://www.theory.cs.uvic.ca/∼cos/inf/neck/NecklaceInfo.html.
  36. E. W. Weisstein, “Totient function,” MathWorld—A Wolfram Web Resource, http://mathworld.wolfram.com/TotientFunction.html.
  37. J. Castro-Gutierrez, D. Landa-Silva, and J. Moreno Perez, “Improved dynamic lexicographic ordering for multi-objective optimisation,” in Proceedings of the 11th International Conference on Parallel Problem Solving from Nature, pp. 31–40, September 2010.
  38. J.-E. Martínez-Legaz, “Lexicographical order, inequality systems and optimization,” in System Modelling and Optimization, vol. 59 of Lecture Notes in Control and Information Sciences, pp. 203–212, Springer, Berlin, Germany, 1984. View at Publisher · View at Google Scholar · View at MathSciNet
  39. R. Betti, M. Asce, A. C. West, G. Vermaas, and Y. Cao, “Corrosion and embrittlement in high-strength wires of suspension bridge cables,” Journal of Bridge Engineering, vol. 10, no. 2, pp. 151–162, 2005. View at Publisher · View at Google Scholar · View at Scopus
  40. R. M. Mayrbaurl and S. Camo, “Cracking and fracture of suspension bridge wire,” Journal of Bridge Engineering, vol. 6, no. 6, pp. 645–650, 2001. View at Publisher · View at Google Scholar · View at Scopus
  41. D. A. Fishbain, J. R. Fletcher, T. E. Aldrich, and J. H. Davis, “Relationship between Russian roulette deaths and risk-taking behavior: a controlled study,” American Journal of Psychiatry, vol. 144, no. 5, pp. 563–567, 1987. View at Publisher · View at Google Scholar · View at Scopus
  42. X. Q. Peng, L. Geng, W. Liyan, G. R. Liu, and K. Y. Lam, “A stochastic finite element method for fatigue reliability analysis of gear teeth subjected to bending,” Computational Mechanics, vol. 21, no. 3, pp. 253–261, 1998. View at Publisher · View at Google Scholar · View at Scopus
  43. H. P. Gavin, “Bicycle-wheel spoke patterns and spoke fatigue,” Journal of Engineering Mechanics, vol. 122, no. 8, pp. 736–742, 1996. View at Publisher · View at Google Scholar · View at Scopus
  44. O. Gerstel, R. Ramaswami, and G. H. Sasaki, “Fault tolerant multiwavelength optical rings with limited wavelength conversion,” IEEE Journal on Selected Areas in Communications, vol. 16, no. 7, pp. 1166–1178, 1998. View at Publisher · View at Google Scholar · View at Scopus