Modeling and Control Problems in Sustainable Transportation and Power Systems
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Xinhan Meng, KeJun Li, Zhuodi Wang, Wenning Yan, Jianguo Zhao, "A Hybrid MMC Topology with dc Fault RideThrough Capability for MTDC Transmission System", Mathematical Problems in Engineering, vol. 2015, Article ID 512471, 11 pages, 2015. https://doi.org/10.1155/2015/512471
A Hybrid MMC Topology with dc Fault RideThrough Capability for MTDC Transmission System
Abstract
This paper proposes a hybrid modular multilevel converter (MMC) topology based on mismatchedcascade mechanism. The blocking conditions of different submodule (SM) structures under dc fault are analyzed and a series double submodule is presented. With seriesdouble submodules and mismatchedcascade submodules, the proposed hybrid MMC can ridethrough the dc side shortcircuit fault and provide an output voltage with the feature of low harmonic content. This hybrid MMC topology can be used in the VSC based multiterminal dc (VSCMTDC) transmission system. The dc fault ridethrough properties of the new structure and the total harmonic distortion (THD) are analyzed compared with the previous fullbridge and clampdouble architectures. An appropriate fault blocking procedure is presented, and a typical fourterminal dc transmission simulation system is given in the power system simulation software. Finally, simulation of steadystate and dc bipolar shortcircuit fault verifies that the MTDC system based on this new hybrid MMC topology is stabilized and can block the dc fault and return the nonfault parts to normal.
1. Introduction
With the development of power electronic technology, the voltage source converter (VSC) based on fullcontrollable electric semiconductor device is widely applied to high voltage direct current transmission field. Compared to the traditional HVDC, VSC based high voltage dc (VSCHVDC) transmission system has the advantages such as flexible power control, reactive power compensation, supplying power to passive network, and forming multiterminal dc network [1–5]. According to the different structures of voltage source converter, VSCHVDC can be divided into two kinds: the low level traditional VSCHVDC and modular multilevel converter based high voltage dc (MMCHVDC) transmission system. MMCHVDC is superior to the low level VSCHVDC in the following aspects: it has lower switching frequency, lower switching loss, and higher scalability; it does not need to switch the serial IGBTs at the same time and can be applied in high voltage occasion. Consequently, it has been rapidly developed for the last few years [6–8].
The present research of VSCHVDC is mostly focused on halfbridge MMC (HBMMC) and its control strategies. However, halfbridge MMC cannot clear the fault current when dc fault occurs because of the freewheeling diode [9, 10]. At the same time, high power dc current breaker for HVDC applications is not sufficiently mature and costeffective [11]. So, when dc fault occurs, the common method is to turn off the whole dc system with ac circuit breakers [12]. This approach costs lots of time and reduces the reliability of VSCHVDC system. To avoid dc fault, cable with low failure rate is used as transmission lines, but this increases the engineering cost and is easily restricted by the working environment. Thus, the present VSCHVDC technology could hardly be used in long distance or multiterminal dc transmission system [13, 14].
To overcome the shortcomings of traditional MMC, different topologies have been addressed by many scholars. References [15, 16] propose an MMCHVDC system based on fullbridge MMC (FBMMC) topology. FBMMC can block the fault current when dc fault occurs. However, as too many IGBTs are needed, under the same dc voltage and power level, FBMMC’s engineering investment and operation cost is high, which limits its application in engineering practice. In order to reduce the IGBT used quantity and make the converter capable of blocking dc fault, a new kind of clampdouble MMC (CDMMC) is proposed [14, 17, 18]. When a fault occurs on the dc side, CDMMC turns off IGBTs immediately and utilizes the diode reversedphase blocking ability to complete the fault handling process. CDMMC needs less semiconductors than FBMMC and also has the ability to block dc fault. However, due to the characteristics of parallel structure, the equivalent capacitance in a bridge arm shows two kinds of states according to the different flows of shortcircuit current. So it requires longer time to cut off the shortcircuit current, and its dc fault blocking ability is inferior compared with FBMMC [14, 19].
The contribution of this paper is to analyze the equivalent states of various MMC topologies under the dc shortcircuit fault and propose an improved MMC topology to improve its performance. Based on the mismatchedcascade mechanism and the principle of dc fault blocking, a hybrid MMC topology which has dc fault ridethrough capability and is very suitable for MTDC system is presented. According to the “handshaking method” of MTDC system [20, 21], the process of clearing dc fault and recovering nonfault lines is explained in detail. Finally, a typical fourterminal dc system is introduced and a simulation model is built to verify the system characteristics under the bipolar shortcircuit fault which is the most serious dc fault.
This paper is organized as follows: after introduction, the dc fault blocking analysis, which includes analyzing the fault blocking principle and the current paths of different submodules under blocking states, is explained in detail in Section 2. In Section 3, a new topology of hybrid MMC based on the mismatchedcascade mechanism is introduced. In Section 4, a fourterminal dc simulation model is built to explain the application of the new hybrid MMC in MTDC transmission system, including the process to remove the fault lines and recover the nonfault lines under the dc fault. This new hybrid MMC used in MTDC system is tested with the steadystate and dc bipolar shortcircuit fault simulations in Section 5. The conclusion of this paper is made in Section 6.
2. Fault Blocking Ability Analysis
2.1. Fault Blocking Principle
An MMC topology consists of two arms per each phase where each arm is comprised of seriesconnected submodules and a seriesconnected inductor. These submodules of each bridge arm can be replaced with an ideal voltage source. After the treatment of presenting network parameter by perunit value normalization, the equivalent circuit under dc fault state is shown in Figure 1.
Considering the upper and lower loops, the dynamics of the converter can be described as follows:where and , , and represent the equivalent values of the inductance, resistance, and transformer leakage inductance.
The dynamics of the dc fault current and voltage are expressed aswhere and represent the equivalent values of the dc side inductance and resistance, represents the equivalent value of the shortcircuit fault resistance, and represents the equivalent value of the capacitance under the fault state.
Combining these aforementioned equations, the following equation can be obtained:where , , and .
Thus, the fault equivalent circuit is a secondorder oscillated discharging circuit. When dc fault occurs, the dc side fault current can be determined by the derivative of (3) at , which is expressed bywhere and are the initial values of and . , , , and .
The shortcircuit fault current can be calculated by (4). The discharge process before converter blocking is an oscillated discharge procedure which has already known the initial conditions. The equivalent value of the capacitance changes after the converter blocking. If and only if the equivalent capacitor voltage under any circuit state is larger than the ac line voltage amplitude, the shortcircuit current can be reduced to zero by the antiparallel diodes. Then, the dc fault would be blocked.
2.2. SM Circuit Topologies under Blocking States
2.2.1. FullBridge Submodule
The fullbridge submodule is as shown in Figure 2(a). The control system sends blocking signals to all the IGBTs on the bridge arms when dc fault is found. The path of the shortcircuit current is shown in Figure 2(b). The SM’s equivalent capacitor voltage after blocking is in the opposite direction with the ac side voltage. Thus, the shortcircuit current is blocked from feeding into the converter. However, because a fullbridge submodule needs four IGBTs, the number of required components is doubled to that of the halfbridge submodule needs. So, the fullbridge submodule based MMC is not costeffective.
(a)
(b)
2.2.2. ClampDouble Submodule
The clampdouble submodule, as shown in Figure 3(a), is constituted by two equivalent halfbridge SMs and an IGBT with freewheeling diode. When the dc side fault occurs, the CDSM is switched to the block mode, as shown in Figure 3(b). The equivalent capacitor voltage can stop the fault current from feeding into the converter. However, the equivalent capacitor voltages of a SM are different when the flow of the fault current changes. If , the voltage is ; otherwise, it turns to be . Correspondingly, the equivalent capacitances are and for each of them separately. Thus, during the dc fault periods, the system charges the SM capacitors repeatedly. This leads to the delay of fault blocking time.
(a)
(b)
2.2.3. SeriesDouble Submodule
As the HBSM has the advantages of having simple structure and mature control strategy and being economical, reliable, and efficient, the seriesdouble submodule (SDSM) presented is based on two HBSMs, as shown in Figure 4(a). Between the two HBSMs, there is an IGBT with freewheeling diode to isolate them. SDSM features are economical, reliable, and efficient as HBSM and can block dc fault. Under steadystate operations, the middle IGBT is turned on, and the SDSM is equivalent to two HBSMs in series. At this point, the SDSM’s control strategy is simple as the HBSM’s. When the dc side fault happens, the control system sends blocking signals to all the IGBTs. As shown in Figure 4(b), no matter how the current flow direction is, the equivalent capacitor voltage of SDSM is , and the voltage direction is opposite to the alternating voltage direction at any moment. So the shortcircuit current from the ac system is blocked, and the SDSM based MMC has the dc fault ridethrough capability.
(a)
(b)
As shown in Table 1, SDMMC needs less semiconductors and has the same dc fault blocking capability compared to FBMMC. As for CDMMC, due to the characteristics of parallel structure, the equivalent capacitance in a bridge arm shows two kinds of states according to the different flows of shortcircuit current, as shown in Figure 3(b). So it requires longer time to cut off the shortcircuit current, and its dc fault blocking ability is inferior compared with FBMMC and SDMMC. The comparison of dc fault blocking time of various MMC configurations is shown in Figure 5. In consideration of the number of semiconductors used and power losses, SDMMC is better than FBMMC. Power losses are represented by the estimated power losses, which is the ratio of converter’s losses (primarily the IGBT switching losses) and the rated capacity of MMC. Among these, the switching losses are calculated by the onoff time and the single switch loss of IGBT. The estimated power losses in Table 1 are under the circumstances when is equal to 10. So SDSM is a kind of good submodule topology applied into MMC structure with dc fault ridethrough capability.

Also, SDSM has a weakness as well as these advantages above. When all the IGBTs are blocked, the semiconductors and need to support doubling the blocking voltage (i.e., ). So the related semiconductors ( and ) need a special design to overcome this larger voltage than other ones. A common method is to be realized by series connection of two semiconductors. In this instance, the number of IGBTs per arm needed by SDMMC is increased from to . It is a little more than CDMMC needed, but still less than FBMMC used. So the power losses produced by SDMMC ( is replaced by the series connection of two semiconductors) are less than FBMMC but are a little more than CDMMC. However, as shown in Figure 5 and Table 1, SDMMC is better than CDMMC in dc blocking time. It will save 25% time than the CDMMC to block the dc fault. Consequently, in consideration of the double blocking voltage problem, the proposed SDMMC still has its special advantages compared with other MMC configurations.
3. Topology of MismatchedCascade Mechanism Based Hybrid MMC
3.1. Application of MismatchedCascade Mechanism
Mismatchedcascade mechanism can be used to improve the quality of step wave. Firstly, it produces a small range of dislocations to the basic waveform. Secondly, it stacks these mismatched waveforms to produce a more meticulous waveform. Mismatchedcascade mechanism based MMC is constituted by adding a mismatchedcascade submodule (MCSM) to the former structure. The MCSM is formed by connecting some halfbridge units in series, as shown in Figure 6.
represents the number of halfbridge units in an MCSM. represents the nominal voltage of the halfbridge unit capacitor, and it must be restricted as
When , , for example, then ; the output voltage waveform in the effect of MCSM and the switching mode of SMs are shown separately in Figure 7 and Table 2. As the upper and lower bridges are symmetrical, the output voltage waveform only considers the condition of .

When the number of halfbridge units in upper bridge’s MCSM is , correspondingly, the number of halfbridge units in lower bridge’s MCSM is ; the output voltage waveform remains precisely unchanged. However, when increases and decreases, on the contrary, the output voltage levels can produce small dislocations, as shown in Figure 7. The FFT analysis demonstrates that the output voltage has a better quality (THD is changed from about 12% to 4%) after the MCSMs are added to the MMC structure.
After the MCSM applied, the number of output voltage levels is changed from to :
When , , for example, the number of output voltage levels will be changed from 21 to 63 after the MCSM applied. And the voltage total harmonic distortion (THD) under different modulation ratio is shown in Figure 8.
Thus, it can be observed that only an MCSM is needed to increase the number of output voltage levels several times over, and the structure of MMC is not changed sharply. This will reduce the harmonic content of output waveform largely.
3.2. Topology of Hybrid MMC
Based on the fault blocking principle shown in Section 2 and the mismatchedcascade mechanism shown above, a hybrid MMC topology is presented here. As stated above, HBSM has the advantages of having simple structure and mature control strategy and being economical, reliable, and efficient. SDSM has the dc fault ridethrough capability. And MCSM can optimize the quality of output voltage waveform. So it is considered to connect them to build a hybrid MMC which has all these advantages. In the hybrid MMC, represents the minimum number of SDSMs which a bridge arm needed. Considering the constraint conditions of dc fault blocking, the equivalent capacitor voltage must be larger than the reversed alternating voltage at any moment. So must follow the principle as follows:where represents the maximum value of ac side phase voltage and represents the voltage of a single capacitor in SDSM. On equal conditions, the reverse voltage is larger when increases, and so the blocking time needed is shorter. Thus, the hybrid MMC needs more time to block the dc fault than the MMC made up by SDSM only. To balance dc fault blocking capacity and economical efficiency, under the premise of meeting the requirement of fault blocking time, the number of SDSMs will be decreased as much as possible. Here is defined to represent the number of HBSMs on a bridge arm, and is the number of SDSMs used. When the total voltage level number is fixed, and should follow the principle as follows:
To determine the appropriate proportional relation of the number of HBSMs and SDSMs, a simulation model for hybrid MMC was built in PSCAD/EMTDC, and the dc fault blocking time in different combinations of and was measured as shown in Table 3.

As the SDSM is constituted by two HBSMs, and the middle IGBT is turned on under steadystate operations, the SDSM is equivalent to two HBSMs in series. So the THDs and the estimated power losses of schemes 1~3 are almost equal. The efficiency of each scheme means each IGBT’s contribution to the total output levels. It is the ratio of the output levels and the number of IGBTs used in a singlebridge arm. From Table 3, it can be observed that scheme 1 has the highest efficiency among all the three schemes since the blocking time is the longest too. However, as all the blocking time is less than 30 ms which is short enough to block the fault, scheme 1 is able to meet the dc fault blocking time requirement when the target is not too strict. Under such circumstances, the required number of IGBTs is suitable, and the hybrid MMC based transmission project is economical.
When MCSM is added, the total voltage level number would be changed from to . is defined to represent the number of halfbridge units in an MCSM. Then, should be processed as
This means that the output voltage level number is increased several times over when adding MCSM to the hybrid MMC.
4. Application of Hybrid MMC in MTDC Transmission System
The multiterminal direct current (MTDC) transmission system can be divided into series, parallel, and hybrid forms, by the different connection modes. Parallel connection mode is the most popular one owing to its characteristics of simplicity, flexibility, and expandability [5]. In this section, a typical parallel fourterminal direct current transmission system is utilized to analyze the procedure of the hybrid MMCMTDC transmission system blocking dc side fault.
Reference [20] proposes a “handshaking method” and its procedure to deal with the dc fault in two levels’ VSCMTDC transmission system. Using this method, the voltage stability and power recovery after failure can be insured. However, as circuit breakers are needed to cut off the shortcircuit current from ac side, the time required to block the fault and recover the rest is too long. Meanwhile, the hybrid MMC presented has the dc fault ridethrough capability by itself, so the hybrid MMC based MTDC transmission system can process the dc fault much faster.
As is shown in Figure 9, hybrid MMC is applied in this fourterminal MTDC. are the disconnecting switches in each dc transmission line. Based on this system, the process of the presented hybrid MMCMTDC removing the fault lines and recovering the nonfault lines under dc side fault is as follows.
Step 1. Each converter monitors the dc side bus voltage and current in real time. Using the dc fault detection method [20, 21], and combined with the system parameters, the control system is able to acquire when the dc fault occurs and which kind of it.
Step 2. After the dc fault is detected, according to the changes of current, voltage, and power flow at the dc side bus of each MMC, the potential fault lines can be detected [22].
Step 3. The disconnecting switches in the potential fault lines are marked, so that the fault lines can be isolated after the dc fault blocking.
Step 4. Blocking signals are sent to the SMs which have the dc fault ridethrough capability in the hybrid MMC. At the same time, all the bypass switches paralleled with other SMs are turned on to protect the semiconductor devices in them. Considering the delay time of detecting fault and blocking IGBTs, the time needed for MMC to deal with the dc fault is within 5~10 ms.
Step 5. The disconnecting switches marked in Step 3 are turned off. According to the simulation results and the dc fault clearing time listed in Table 3, the switches should be disconnected at about 30 ms after the converters receive blocking signals.
Step 6. The control system sends unblocking signals to the converters to unblock all the IGBTs in MMC and turns off the bypass switches in Step 4.
Step 7. The converters are set to run in constant dc voltage control mode until the dc bus voltage increases to its rated value. At the moment, the disconnecting switches in the potential fault lines measure the voltages on their both sides. If the voltage difference is less than a certain value, the switch would close itself.
Step 8. After the switches in the nonfault lines closed, all of the converters are set to their original modes. And then, the fault line is isolated and the nonfault lines are returned to service. The hybrid MMCMTDC transmission system reaches a new steady state under the presupposed operating conditions.
5. Simulation Analysis
To verify the reliability of the represented hybrid MMCMTDC transmission system and its capability to block dc fault, a fourterminal MTDC simulation model is built in PSCAD/EMTDC. Where MMC1 uses the constant dc voltage and ac voltage control mode, MMC2 adopts the dc voltage drop and constant ac voltage control mode; both MMC3 and MMC4 take the constant active and reactive power control mode. Each bridge arm in hybrid MMC is consisted by 12 HBSMs, 4 SDSMs, and 1 MCSM, and an MCSM is made up by 4 halfbridge units. According to (9), the maximum number of output voltage levels is changed from 21 to 105 after MCSM added. It reduces the harmonic content of output waveform immensely.
The parameters of this hybrid MMCHVDC simulation system are listed in Table 4. The power direction flows into the converter are set as positive. The converter transformers adopt the YNd11 connection scheme. The converters are connected by high voltage direct current cable, and the unit of distance impedance is 0.01 Ω/km.

5.1. SteadyState Simulation and Analysis
When the hybrid MMCMTDC transmission system is under the steadystate operation, the active power of MMC3 is changed from 50 MW to 80 MW and the active power of MMC4 is changed from 100 MW to 50 MW at 0.6 seconds. The active power of MMC3 is changed from 80 MW to 100 MW and the active power of MMC4 is turned from 50 MW to −50 MW at 0.8 seconds. The reactive power of MMC4 is turned from −50 Mvar to 50 Mvar at 1.0 second. The active power of MMC3 and MMC4 is resumed to 80 MW and 100 MW at 1.2 seconds. The simulation waveforms are shown in Figure 10.
(a)
(b)
(c)
As shown in Figure 10, since MMC1 adopts the constant dc voltage control mode and the power change is within the adjustable range, the active power imbalance is compensated by MMC1 at the time of 0.6 seconds. The active power of MMC4 is changed significantly at the time of 0.8 seconds and the power flow turns to the opposite direction. According to the dc voltage control mode of MMC2, both MMC1 and MMC2 are needed to compensate the active power and stabilize the dc voltage. Meanwhile, the dc voltage of MMC4 is changed from slightly larger to less than 400 kV, so that MMC4 can absorb the active power from the system. At the time of 1.0 second, the reactive power of MMC4 changes from −50 Mvar to 50 Mvar and the dc voltage of MMC4 tends towards stability after a slight oscillation. During this process, the other converters’ dc voltages always keep stable. It means that the change of reactive power rarely has influence on the stability of the dc system. At the time of 1.2 seconds, the power of MMC3 and MMC4 recovered, so MMC1 and MMC2 changed their output to maintain the system stability. During the whole process, after the changes of parameters, the system restores to a steady state within a short time (less than 50 ms), and the fluctuation is within ±1%. All of these indexes meet the requirements of the system stability.
5.2. Simulation of the DC Bipolar ShortCircuit Fault
To verify the capability of the new hybrid MMCMTDC under dc side fault and analysis of the characteristic of nonfault lines’ recovery, a dc fault in lines 12 close to MMC1 is set at the time of 2 seconds. The dc fault can be divided into three kinds: monopolar grounding fault, tripping fault, and bipolar shortcircuit fault. In all the three kinds of dc faults, the bipolar shortcircuit fault causes the most serious effect [23]. So, to make the focal points stand out, only bipolar shortcircuit fault is simulated and analyzed in this section. Combined with the control strategy presented in Section 4, a hybrid MMC based fourterminal dc transmission system is built in PSCAD/EMTDC, and the waveforms of fault state simulation are shown in Figure 11.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
As shown in Figures 11(a) and 11(b), after the dc fault occurs, the hybrid MMC blocks itself; then the active power and reactive power reduce to zero within 35~40 ms. When the converter is unblocked, the dc voltage recovers to 400 kV; then the active power and reactive power turn to their new steady states. Due to the fact that the fault lines have been isolated and that the system network parameters have been changed, the transmission power of MMC1 and MMC2 changes from the original state to a new steady state.
As shown in Figures 11(c) and 11(d), after the dc fault occurs, the fault current increases sharply and the dc voltage falls off due to the capacitor discharge and the ac side through fault current. Then, the control system sends blocking signals to block the hybrid MMC. After blocking, the capacitor voltage stops the ac current from flowing into the dc side. Then, the shortcircuit current and dc voltage go down to zero, respectively. After that, the disconnecting switches are turned off, and unblocking signals are sent to the converters. At the same time, all the converters are set to run in constant dc voltage control mode until the dc bus voltages increase to their rated values. At this moment, the disconnecting switches in the nonfault lines detect the voltage differences are less than the set value and close themselves. At last, all the converters are set to their original modes and rises to a new steady value.
As shown in Figures 11(e) and 11(f), the SMs’ voltages stay near the rated voltage value 20 kV. So, after the fault line is removed, there is no need to charge the capacitors in the SMs again, and then the recovery time will not be too long.
As shown in Figures 11(g) and 11(h), the ac side current decreases to zero during the blocking time and recovers to the steady value when the system is put into operation again. During this process, there is no offlimit condition, and the ac voltage variation is less than 5%. So, all the results indicate that the dc fault can hardly influence the ac system and the new hybrid MMCMTDC transmission system is stable during the fault process.
6. Conclusions
In this paper, the mismatchedcascade mechanism and dc fault blocking principle are implemented in a hybrid MMC topology. Firstly, the dc fault blocking principle and different topologies of submodules are presented to analyse the fault ridethrough capability. A new kind of seriesdouble submodule is proposed. Based on this submodule, the MMC can block dc fault and the number of semiconductor devices is reduced. A new hybrid MMC topology constituted by halfbridge SM, seriesdouble SM, and mismatchedcascade SM is proposed. The effect of this kind of MMC to block dc fault is verified by simulation in PSCAD/EMTDC. Then, an MTDC transmission system based on this hybrid MMC and its process to remove the fault lines and recover the nonfault lines are presented. Finally, a fourterminal dc simulation model is built. Based on this model, both steady state and fault state are analyzed by simulations. According to test results, it is shown that dc system based on this new kind of hybrid MMC can block the dc fault accurately and quickly. And the nonfault parts can be restored to normal operation. With the fault blocking ability and feasible control strategy, this hybrid MMC presented can be applied into connecting the renewable source to power grid and forming multiterminal dc network.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the republication of this paper.
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Copyright © 2015 Xinhan Meng et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.