Research Article | Open Access
A Statistic-Based Calibration Method for TIADC System
Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). Therefore, a statistic-based calibration method for TIADC is proposed in this paper. The average value of sampling points is utilized to calculate offset error, and the summation of sampling points is used to calculate gain error. After offset and gain error are obtained, they are calibrated by offset and gain adjustment elements in ADC. Timing skew is calibrated by an iterative method. The product of sampling points of two adjacent subchannels is used as a metric for calibration. The proposed method is employed to calibrate mismatches in a four-channel 5 GS/s TIADC system. Simulation results show that the proposed method can estimate mismatches accurately in a wide frequency range. It is also proved that an accurate estimation can be obtained even if the signal noise ratio (SNR) of input signal is 20 dB. Furthermore, the results obtained from a real four-channel 5 GS/s TIADC system demonstrate the effectiveness of the proposed method. We can see that the spectra spurs due to mismatches have been effectively eliminated after calibration.
In the past decades, modern electronic systems have been revolutionized with fast developing of digital signal processing techniques which offer unprecedented performance and adaptivity. However, the application of DSP is hindered by difficulty in capturing ultrafast signal in high speed electronic systems. The capturing of ultrafast electrical signals is a difficult problem that requires high speed analog-to-digital converters (ADCs). Because of the limitation of fabrication technology, maximum achievable sampling rate of single ADC is limited. Thus, time-interleaved technique proposed by Black and Hodges  that results in a time-interleaved ADC (TIADC) is widely used to increase sampling rate.
Ideally, TIADC is formed by identical parallel ADCs (sub-ADC or channel). Each ADC should have the same gain and offset and should be operating at the equally displaced sampling time instants. However, due to fabrication dispersion, mismatch errors in TIADC system are inevitable. Channel mismatches, such as gain mismatch, offset mismatch, and timing skew mismatch, will result in distortion of sampled waveform and degrade the performance of TIADC. This has been proved in some contributing works [2–5].
A lot of methods have been proposed to calibrate the mismatches in TIADC [6–20]. Blind calibration techniques have been researched in [7–11]. The attractive advantage of blind calibration is that it does not require a dedicated calibration period. However, blind methods typically require a very high computational cost. In , a FFT-based gain and offset error calibration method is proposed, but as we know, many multipliers and other resources are needed in FFT (fast Fourier transform). An adaptive calibration method is proposed in , where a reference signal is introduced to identify mismatch parameters. In , a synthesis calibration method is proposed. This method can calibrate three mismatches simultaneously, but the calibration process is too complex, and it takes a long time for calibration. Some digital compensation methods for timing skew calibration, such as fractional delay filters , multichannel filters , Lagrange polynomial interpolation , and perfect reconstruction , are presented, but timing skew must be estimated before these methods are employed to compensate timing skew. A code-density based timing skew detection method is proposed in , where an auxiliary circuit is added to detect timing skews. A timing skew calibration method based on zero-crossing is proposed in , where a zero-crossing detector is added for calibration.
A very easy calibration method is proposed in this paper. Compared with the previous methods, it has the following contributions. Firstly, this method can obtain gain and offset error accurately by simple addition operation. Secondly, the identification of timing skew is not required. This avoids the complicated measurement or estimation of timing skew. Finally, no auxiliary hardware circuits and filters are added for calibration. Thus, the implementation cost is reduced.
This paper is organized as follows. Section 2 gives the model and impact of TIADC mismatch. The calibration method is derived and explained in Section 3. In Section 4, the implementation of proposed calibration method is given. Section 5 shows the simulation results, and experiments results obtained from real four-channel 5 GS/s TIADC system are presented to validate the proposed method. Section 6 is dedicated to the conclusion of our work.
2. Model and Impact of TIADC Mismatch
In this section, to propose the calibration method, the mismatch model of TIADC is depicted first. Then, the output of sub-ADC is derived. Finally, the output spectrum of TIADC is also calculated to demonstrate the impact of TIADC mismatches.
As shown in Figure 1, a TIADC system consists of parallel ADCs. Each ADC operates with a sampling frequency of and samples the input in turn, so the TIADC system has a sampling frequency of . For a nonideal TIADC, mismatches are inevitable, each ADC has different gain and offset, and the sampling time intervals between adjacent ADC are not equal. Therefore, in Figure 1, gain, offset, and sampling instant of are denoted by , , and , respectively.
As we know, for an ideal TIADC, the sampling instant of is where refers to the sample period of TIADC system. Considering the relative timing skew in , sampling instant of can be denoted as Thus, for a sinusoidal , the output of TIADC will be where refers to input signal frequency and refers to the normalized angular frequency. In the following part of this paper, we assume that is a sinusoidal signal, and shown in (3) will be utilized.
Figure 2 shows the timing skew in a four-channel TIADC. As shown in Figure 2, refers to the absolute timing skew of channel and refers to the sampling time interval between channel and channel . These notations will be used in the following description.
According to the principle of TIADC, the sampling impulse of TIADC can be represented as Thus, considering mismatches in TIADC, the output signal of TIADC is where and refer to gain error and offset error, respectively. The Fourier transform of (4) is and the Fourier transform of gives thus, the Fourier transform of (5) can be calculated as where . From (8), we can see that if offset error is not zero, spectrum spurs will appear at . For a sinusoidal whose angular frequency is , spectrum spurs due to gain and timing skew will appear at . What is more, amplitudes of spectrum spurs due to gain error are only relative to the value of gain error, while the amplitudes of spurious peaks introduced by timing skew are determined by both the value of timing skew and the input frequency.
3. Statistic-Based Calibration Method for TIADC
In this section, offset, gain, and timing mismatch calibration methods are introduced separately.
3.1. Offset Mismatch Calibration
Assuming that infinite sampled points of are obtained, it is easy to see from (3) that the average value of these points is Considering sampling points are obtained, the average value of these points can be written as When is large enough, approaches ; thus, From (11), we can know that the offset of each ADC can be obtained by calculating the average value of sampling points. In general, one chooses channel 0 as a reference and then matches all other channels to this reference channel. Therefore, offset mismatch can be calculated as
3.2. Gain Mismatch Calibration
For convenience, a simple sinusoidal signal is used in the following derivations. Supposing that the analog signal is sampled with a sampling period , the sampling points will be . Let us assume that sampling points are obtained in a half cycle of the sinusoidal signal; thus,
The summation of these sampling points can be written as
When is very large, approaches zero. For this case, according to the definition of integral, the summation can be changed to integral. Therefore, we have Finally, from (13)–(15), we can get Furthermore, for sampling points which include one cycle of the sinusoidal signal, it can be obtained that where represents the absolute value. It is clear that the initial phase of the sinusoidal signal does not affect . Therefore, from (3) and (17), it gives that where is calculated as (11). From (18), it can be seen that the gain is relative to . Without loss of generality, we choose channel 0 as a reference; thus, the gain error can be calculated as
It is noted that the premise of (15) is that is large enough. Considering that the frequency of input signal is and the TIADC system has a sampling frequency of and channels, for one subchannel we can obtain that Thus, to make large enough, the sampling rate should be much larger than signal frequency. However, if is large enough, the sampling points will cover many cycles of the signal. Assuming the sampling points obtained in different cycles will be different. Then, as random equivalent sampling, we can use the sampling points obtained from different cycles to reconstruct one cycle of the input signal. Therefore, as long as is large enough and (21) is satisfied, the gain error can be estimated accurately by (19).
3.3. Timing Mismatch Calibration
After offset and gain mismatches are calibrated, we can assume that for any , and the gain of each channel is . Under this assumption, the product of two adjacent channels can be written as By using the product-to-sum formula, (22) is changed to When sampling point number approaches infinity, the average value of the second part of (23) will be zero. Therefore, the average value of is If there is no timing skew in all channels, for any , will be . According to the Nyquist criterion, the range of is . In this range, cosine is a monotone decreasing function. Thus, if is larger than , it implies that the sampling interval between channel and channel is smaller than standard value . Conversely, it means that the sampling interval is larger than . Therefore, can be used as a metric to calibrate timing skew.
Assuming that sampling points are used to calculate , the estimated value of is where In order to get an accurate estimation value of , suitable and are needed to make approach zero. Firstly, must be large enough. Secondly, when the angular frequency of is , will not approach zero. Thus,
As mentioned above, is utilized to calibrate timing skew. When there is no timing skew, the reference value of is . However, it is not easy to get accurately, so we cannot calibrate timing skew simply by adjusting and to make approach . An iterative method is proposed here.
First, for each are calculated as Then, is adjusted to make be equal to . is adjusted as where represents the residual timing skew of channel after times iteration, refers to the adjustment step, and refers to the adjustment direction. If is larger than , is +1; otherwise, is −1. is decided by the adjustment method of timing skew. There are two methods to adjust . One method is adjusting the sampling clock of channel directly. This method needs digital control delay element (DCDE) in ADC or clock generation circuit. The other method is making use of fraction delay filters . After this step, all except are equal. What is more, when is equal to , it is obtained from (24) that By substituting into (30) and after some recursive derivations, we can get
Furthermore, is adjusted to make be equal to other . It is clear that should be adjusted. However, once is modified, not only but also is changed. Therefore, considering the residual timing skew shown in (31), to keep all except equal in this calibration step, each is adjusted as If is larger than other , it means that is smaller than other ; thus, should be decreased to increase and is −1. Conversely, should be decreased, and should be increased and is +1. When all have the same value, the calibration is finished.
The calibration process of four-channel TIADC can be shown as in Figure 3. At the beginning of calibration, it is assumed that the timing skews are [0, −0.02, −0.01, 0.01]. Because is smaller than , is decreased. After iterations, and are equal, and the timing skews are [0, −0.01, −0.02, 0.01]. Then, is also decreased since is smaller than . After iterations, and are equal, and the timing skews are [0, −0.01, −0.02, −0.03]. Finally, and are compared. Because is larger than , is increased by . To keep and be equal to , and are increased by and , respectively. When and are equal, the iteration is stopped and the calibration finishes.
The proposed calibration method is implemented in a 5 GS/s TIADC-based data acquisition system (DAS), whose diagram is shown in Figure 4. The whole system is composed of front end circuits of ADC, clock generation circuits which include crystal and phase locked loop (PLL), ADC, field programmable gate array (FPGA), and digital signal processor (DSP). FPGA is employed for sampled data receiving and storage. In FPGA, the sampled data from ADC are received by input double data rate (IDDR) elements firstly. Then, the sampled data are stored in FIFO (fist in fist out) which is built by memory in FPGA. At last, the sampled data are transmitted to DSP. Because the calculation speed of FPGA is faster than DSP, the addition and multiplication operation needed for calibration are also implemented in FPGA. DSP48E elements in Xilinx FPGA are utilized to implement addition and multiplication operation. The whole system is controlled by DSP.
The part number of 5 GS/s ADC is EV8AQ160, which consists of four 1.25 GS/s ADC cores. The simplified block diagram of this ADC is also shown in Figure 4. It can be seen that there are offset, gain, and phase adjustment elements in ADC. These adjustment elements are controlled by digital control word (DCW), which is sent from FPGA by serial peripheral interface (SPI). The adjustment steps of offset, gain, and phase are 0.2 LSB, 0.14%, and 110 fs, respectively.
The calibration process is conducted as follows.
First, the average value of sampled data of each channel is calculated, and offset error is obtained by (12). After the offset error is obtained, it is corrected by sending DCW to offset adjustment element. The DCW is calculated as where the superscripts and refer to new DCW and original DCW, respectively.
Secondly, (19) is utilized to obtain gain error. Gain error is corrected by gain adjustment element, whose DCW is calculated as
Finally, timing skew is calibrated. Phase adjustment element is used to adjust timing skew in the process of iteration. The calibration of timing skew has been discussed in Section 3. Timing skew is adjusted by phase adjustment element, and the adjustment step is 110 fs. When all are equal, the calibration is finished.
5. Experimental Results
A four-channel 5 GS/s TIADC system is simulated to present the performance of proposed method in the following part of this section. Zero-mean Gaussian white noise is added to each channel. The offset, gain, and timing skew errors are set as , , and , respectively. The number of sampling points used for calibration mismatches is selected to be 20000.
First, two experiments are carried out to demonstrate the estimation accuracy of offset and gain error. One experiment is to evaluate the impact of noise on the estimation accuracy of the proposed method. The signal frequency is set to 600 MHz. As shown in Figures 5 and 6, the proposed method can estimate offset and gain error accurately in a wide SNR range from 20 dB to 60 dB. The other experiment aims at evaluating the impact of signal frequency on the estimation accuracy of the proposed method. The SNR is set to 45 dB. From Figures 7 and 8, it is shown that the proposed method has high estimate accuracy in a wide frequency range from 10 MHz to 620 MHz except for some special frequencies shown in (21). It should be noted that Figures 5 to 10 are obtained by some discrete points. In Figures 5, 6, and 9, the step of SNR is 0.4 dB. The step of frequency in Figures 7, 8, and 10 is 10 MHz.
Secondly, the performance of timing skew calibration is demonstrated. Although timing skew is calibrated directly without estimation, after the calibration is finished, the estimated timing skew can be calculated as where refers to the iteration times when calibration is finished. We calibrate timing skew after offset and gain errors are corrected by the proposed method. As offset and gain error, the impacts of SNR and signal frequency on calibration performance are researched, respectively. The estimated timing skews versus SNR and signal frequency are shown in Figures 9 and 10, respectively. From Figure 9, where the signal frequency is set to 600 MHz, it can be seen that is very close to real timing skew in a wide SNR range from 20 dB to 60 dB. Thus, it is concluded that the proposed method can calibrate timing skew accurately in a wide SNR range. Similarly, it is seen from Figure 10 that timing skew can be calibrated with different signal frequency. It should be noted that the proposed method does not work well at some frequencies as shown in (27). Because Figure 10 is obtained by discrete points with a step of 10 MHz, these frequencies are not shown.
Finally, the spectra before and after calibration are shown in Figures 11 and 12. It is shown that after calibration, the spectrum spurs due to mismatches are degraded greatly. This proves the good performance of the proposed method.
5.2. Testing Result of 5 GS/s TIADC System
In this part, the experiment results got from a real 5 GS/s TIADC system, whose diagram is shown in Figure 4, are shown to demonstrate the effectiveness of the proposed calibration method. Figure 13 shows the experiment board of 5 GS/s TIADC. The proposed method is implemented in this system. The main chips which include ADC, FPGA, and DSP are marked in Figure 13. The signal is input by a pair of SMA (Sub-Miniature-A) connectors and then sampled by ADC. The main function of FPGA is sampled data storage. All sampled data are stored in FIFO built by Block RAM (random access memory) of FPGA. In addition, as mentioned in Section 4, the proposed calibration method is also implemented in FPGA. The main function of DSP is system control. ADC and IDDR modules shown in Figure 4 are all controlled by DSP. Moreover, when the FIFO in FPGA is full, the sampled data are transmitted to DSP for analysis.
Since the real mismatches in the system are unknown, the spectra before and after calibration are utilized to prove the effectiveness of the proposed method. From the comparison of Figures 14 and 15, we can clearly see that the spectrum spurs due to the mismatches have been effectively eliminated. These experimental results prove that the proposed method works very well in real system.
The mismatches in TIADC degrade the performance of the system. In particular, in high speed TIADC system, small mismatches will introduce big spectrum spurs. A new calibration method is proposed for a four-channel 5 GS/s TIADC in this paper. It can calibrate mismatches accurately with different SNR and signal frequency. This method can be easily realized in a real system with low cost. It especially suits high speed digital storage oscilloscope and other systems where TIADC-based high speed data acquisition is used.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
This work was supported by the National Natural Science Foundation of China (no. 61301263 and no. 61301264), the Specialized Research Fund for the Doctoral Program of Higher Education of China (no. 20120185130002), and the Fundamental Research Fund for the Central University of China (nos. A03007023801217 and A03008023801080).
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