Neurospace Mapping Modeling for Packaged Transistors

Table 1

Training data and test data for DC and S-parameter modeling of LDMOS transistor.

		(V)	(V)	freq (GHz)
DC Simulation	Training Data	2.6:0.1:3.2	0:2:32
	Test Data	2.6:0.1:3.2	1:2:31
S-Parameter Simulation	Training Data	0:1:1	8:4:24	1.7:0.028:3.1
		2.5:0.1:2.8	30
		0:0.2:2.2	28
		2.3:0.1:2.8
	Test Data	0:1:1	10:4:26	1.7:0.028:3.1
		2.5:0.1:2.8
		0.1:0.2:1.1	28
		1.5:0.2:2.1
		2.45:0.1:2.75