Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Figure 5

The experimental results of embedding “Room” in “Girl.” (a) The cover image “Girl” of size 256 × 256; (b) secret image “Room” of size 128 × 256; (c) the stego image produced by software implementation; (d) the stego image produced by the proposed FPGA design; (e) the secret message extracted by software implementation; (f) the secret message extracted by the proposed FPGA design.

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