Embedded FPGA Design for Optimal Pixel Adjustment Process of Image Steganography

Table 2

Comparison of execution time and speedup for embedding “Lena.”

Execution time (seconds)			Speedup
	software	FPGA
1	0.116042	0.013110	≈8.85
2	0.120556	0.013110	≈9.20
3	0.143214	0.013110	≈10.92
4	0.199567	0.013110	≈15.23