Mathematical Problems in Engineering

Mathematical Problems in Engineering / 2019 / Article
Special Issue

Advanced Mathematical and Numerical Methods in Control and Optimization for Smart Grids

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Research Article | Open Access

Volume 2019 |Article ID 5930548 | 10 pages | https://doi.org/10.1155/2019/5930548

Emulator Based on Switching Functions for a Dual Interleaved Buck-Boost Converter

Academic Editor: Zhan Shu
Received15 Mar 2019
Revised14 Jun 2019
Accepted03 Jul 2019
Published04 Aug 2019

Abstract

Under the unavailability of some components of a complex system, the Hardware In the Loop (HIL) tool allows the emulation of other subsystems. When these devices are not available, a customized emulator can be developed based on the Piecewise Linear Model (PWLM) and a numerical method for solving the differential equations system. However, these implementations require the use of a Field Programmable Gate Array (FPGA) with extensive hardware resources. In this article we propose the use of switching functions for the modeling of power converters of a Hybrid Power System (HPS), allowing the reduction of hardware resources of the FPGA, and the number of steps per switching cycle is increased. The results are compared with SABER simulations and a PWLM evaluated with the Euler method.

1. Introduction

Frequently during the development of a complex system there are multiple subsystems under study; this represents a challenge for the rapid evolution of large projects. With the help of an emulator, multiple components can be developed quickly and efficiently; these tools are called Rapid Control Prototyping (RCP) or HIL. The HIL simulation is a form of simulation of real time; its initial use was in flight simulators and in missile guides, and nowadays its use has been extended to power electronics [1]. HILs are based on two technologies: microprocessors and FPGA. The disadvantage of the microprocessor-based emulators is that sequential logic would require clocks of the order of 1012Hz to match the FPGA concurrence with clocks of the order of 106Hz that would perform the same number of operations [2]. The applications in power electronics are the development of the train power system [3], ships [4], electric vehicles [5, 6], and microgrids [79], achieving in the best of cases a step size of the order of 10ns, if the numerical representation is sufficiently accurate to reduce the error by truncation.

It is observed that the development of a HIL requires the mathematical model that describes the behaviour of the system; that in the case of power converters refers to the equations that solve the electrical network. The hardware resources of the FPGA depend on the model to be implemented, the synthesis procedure, and the format of the arithmetic: in Fixed Point (FXP) or Floating Point (FP). In [10] to model an NPC converter, the network equations were described with the Modified and Augmented Node Analysis (MANA), obtaining the state equations. In [11] to model a three-phase inverter, the network equations were described under the Associated Discrete Circuit (ADC). In [12] the average value method was used to calculate the output value of a three-phase interleaved converter. In [3, 1319], equations are used in the state space to describe the behaviour of different topologies of power converters. However, in order to be implemented, an FPGA with wide range of resources is required; around 65000 Look Up Tables (LUT) to obtain a step size of the order of 5ns, in some cases multiplex arithmetic operations can reduce the size between 15000 and 6000 LUT, with a cost of increasing the step size to 250 ns [18]

In this article, the model based on Switching Functions (SF) for a Dual Interleaved Buck-Boost Converter (DIBBC) with interphase transformer (IPT) was developed, and the hardware implementation was made for an FPGA of limited resources. Likewise SABER simulations results were compared with a PWLM and this proposal. It was observed that the difference between models is minimal; however, in the hardware implementation the difference is drastic. In addition, it was noted that the step size is only restricted to the core speed of the FPGA.

2. Switching Functions Model for DIBBC

2.1. The DIBBC

Figure 1 shows the diagram of a DIBBC composed of a DC voltage source, , a switch bridge Q1, Q2, D1, D2, an (IPT) that includes L1 and L2 where L1 = L2, a common inductor , an output capacitor C, and a load R [20].

2.2. Operation Principle

The circuit operates under the state of transistors Q1 and Q2, presenting two possible permanent state operation regions: D < 0.5 and D > 0.5; the main waveforms are depicted in Figure 2, in (a) - (k) corresponding to D < 0.5 and in (l) - (v) to D > 0.5. In (a) and (l) the signals of the states of the transistors Q1 and Q2 and and are observed for the fixed frequency (1/T) and a phase shifted between them of T/2 and a balanced duty cycle, D. (b) and (m) show the voltages in the nodes and . In (c) and (n) is the differential voltage = - . produces the current in the differential inductor or IPT (d) and (o). (e) and (p) correspond to the voltage in the common inductor . The currents in the common inductor are shown in (f) and (q), the currents in L1 and L2 are (g) and (h), and the currents in diodes and are shown in (h) and (s). The currents of Q1 and Q2 are shown in (i) and (v). The currents in (j) and (u) are the sum of the currents in diodes D1 and D2, and the current in the capacitor in (k) and (v).

Figure 3 shows the nine possible configurations of the DIBBC. The configurations from I to IV, Figures 3(a)3(d), correspond to Continuous Current Mode (CCM), the other five configurations are presented in the DCM, and the Discontinuous Current Mode (DCM) configurations V to IX are shown in Figures 3(e)3(i); the DCM occurs when iL1 = 0 or iL2 = 0; under these conditions iD1 = 0 or iD2 = 0.

2.3. Switching Functions Model for a DIBBC

In each configuration of the circuit, the voltages of the nodes and , which depend only on and , can be established by the product of The vectors are the voltages in the and nodes: , and the vector is the supply voltage and the capacitor voltage : . is a transformation matrix for each configuration that is called Voltage Switching Matrix. For the currents of transistors Q1 and there is a current vector : , and for the currents of the diodes, is . The current vector of the inductors is ; after , , and it can be obtained through the Current Switching Matrices MIQ and MID shown in (2) and (3), respectively. Equation (1) is called voltage switching function () and (3) is called current switching function ():Table 1 shows the MV and MID matrices for each configuration of the circuit; it indicates that the conditions for each configuration are presented and shade the configurations of the CCM. MQ is excluded because at the moment it is not of interest for this work.



The current in can be divided into two when applying the superposition principle: the current that produces the voltage in node A: and the current that produces the voltage in node B: . The voltages in CCM for , , L1, and L2, are given by (4), (5), (6), and (7), respectively, and are obtained from the node analysis between A, B, COM, and GND of the circuit of Figure 1, for which L1 = L2 must be considered.In DCM the voltages in , , L1, and L2 are given by (8), (9), (10), and (11), respectively:Equations (4) to (11) are the interactions in the voltage in the inductor network between nodes A, B, COM, and GND, and they are called . The network of inductors is formed by an interphase transformer (IPT) with the branches L1 and L2 and a common inductor, , the current proper to the IPT iLS is obtained by means of (12) where is the vector and L−1 is the inverse matrix of the inductances of the transformer and is the vector . and are given by (13) and (14), respectively,The currents iL1 and iL2 are given in (15) and (16), respectively. This set of equations are the interaction of the currents in the inductor network and are called :In the DCM, L1 and L2 stop behaving like a transformer and become an inductor when leaving one of its branches at high impedance, so we can do vL1 = vL2 = 0. Observing the sets of (4) and (8), (5) and (9), (6) and (10), and (7) and (10), we have the common factors , , , and , respectively, and we can summarize (4) to (11) in Table 2, where we have the common factor for each inductor voltage and gain factor.


CCM  
  
(Config. I to IV)
DCM  
  
(Config. VI to IX)
Common factor

0
0

The balance of the current is described by (17) and (18); (17) corresponds to the current coming from diodes D1 and D2 and (18) corresponds to the current injected into the RC output network.If and are substituted in (18) and the equation is reordered, then (19) is obtained:If (19) is integrated, (20) is obtained, which would be the expression for modeling the output voltage Equations (1) to (20) and Tables 1 and 2 describe the system model; if you see each equation as a function of input output you can build a block diagram. This diagram is shown in Figure 4.

2.4. System Discretization

The system of Figure 4 is in the time domain; the Laplace transform must be applied to convert it to the domain of the complex variable . In this diagram, with the exception of the integrators, all are arithmetic operators or gains, so the discretization consisted of replacing the integrators with discrete integrators of the block diagram. The discrete integrator that was used in this work has a delay physically feasible, and the transfer function of integration is given in equation (21): Equation (21) is discretized by applying the -transform, obtaining the transfer function of an integrator shown in (22), where is the sampling period:Equation (22) corresponds to an integrator without delay; an integrator with delay according to the delay theorem of the z transform is shown in In Figure 5 a block diagram of the discrete model of the circuit of Figure 1 is shown.

3. Hardware Implementation

For implementation there is a card with a low-end FPGA Altera Cyclone IV E model EP4CE22F17C6N with 22320 LUT. The manufacturer provides the tool to develop systems called Quartus Prime, which allows the implementation of logic and arithmetic, in two languages of hardware description: VHDL and Verilog.

3.1. Arithmetic

Using the tool for IP development (Intellectual Property) of Quartus Prime called LPM Mega Wizard, the additions, subtractions, and multiplications of the model of Figure 4 were implemented. It was decided to use fixed point arithmetic with the format Q (64.32), having 32 bits for the integer part and 32 for the fractional part. The advantage of using fixed point is that the implementation in hardware does not require sequential operations and allows all operations to be performed concurrently. The decision to use the fixed point format was made taking into account the dynamic range of the signals and the error of the representation of the constants of the system. With this format, the truncation error of the representation of the constants is less than 0.0005%. In Results, an error analysis will be shown over time.

3.2. Switching Functions

Only in the case that there are two possible states such as that of the switches, in hardware you can replace that switch represented by a product in the switching function by a multiplexer, like the functions of (1) to (3). Figure 6 shows how the switching function was implemented. It is observed that the products are replaced by multiplexers, which are controlled by the configuration multiplexers, which allow the input of the coefficients of the switching matrices. A 64-bit multiplier in hardware for the CYCLONE IV occupies a space of 4352 LUT, while a 64-bit multiplexer occupies only 64 LUT, which represents a reduction of 68 times the hardware space.

4. Results

Four simulations were carried out, the first using a simulator for physical systems, which in this case was SABER 2.4, the second simulation using PWLM evaluated by the Euler method in MatLAB 2015a, the third being the switching functions using a SIMULINK 2015a model and evaluated by the Euler method, and the fourth being the embedded model of the switching functions with the RTL simulation tool included in Quartus Prime 18.00. Table 3 shows the values of the simulation parameters. SABER is a very accurate simulator so it will be the reference to calculate the error. The state variables of the PWLM are , , and , so the graphs for them are displayed. Figures 7, 8, and 9 show the results of the simulations for the time from 0 ms to 10 ms: (a) corresponds to the four simulations, (b) corresponds to the error of the PWLM, the SF evaluated in SIMULINK, and SF evaluated by the FPGA all with respect to SABER, (c) is a zoom between 9.50 ms to 9.55 ms, and (d) is a zoom of the error for the interval of (c). When the system is in steady state it is observed that the errors between the SFs overlap without diverging. The error for at t = 9.526 ms for the PWLM is under 1.09%, for both SFs it is 1.22%, the error for at t = 9.526 ms for PWLM is 0.83%, and for SFs it is 0.63%; the error for at t = 9.526 ms for PWLM is 0.45% and for SFs it is 0.44%. It should be noted that the circuit enters the DCM in two regions: when the circuit is turned on at t = 0s and during the transient in the interval t = 159µs to t = 413µs. The system reaches the steady state at t = 3.5 ms.


ParameterValue

350 V
75 kHz
150 MHz
45%
4 Ω
38 µH
7 µH
95 µF

In terms of hardware implementation, a PWLM for the DIBBC would occupy a space of 79552 LUT in a Cyclone IV. In the case of the switching function model it deals with 9738 LUT (43.63% of the resources of the available card), depending on the Quartus Prime synthesis reports. Other embodiments were made for the PWLM by multiplexing the multipliers: one was multiplexing one row of equation and another was multiplexing rows of matrix. The results are shown in Table 4.


ImplementationSampling FrequencyNumber of steps per switching cycle MultipliersResources FPGA
(CYCLONE 4 22K)

PWLM multiplier multiplexed in equation row52.5 MHz700314.67%

PWLM multiplexer multiplexed in matrix row105 MHz1400989.60%

SFM150 MHz2000543.63%

5. Discussion

In order to implement a HIL based on a PWLM whose step size is less than 10 ns in an FPGA, extensive hardware resources are required. It is observed that when using a model based on switching functions and fixed point arithmetic with a high resolution, the space in hardware for its implementation is drastically reduced, allowing the use of a FPGA with few resources and with accuracy similar to that of other implementations and the step size is restricted to the core speed of the FPGA. This implementation is intended to be used for the development of a hybrid power system, since it is required to embed in a FPGA the models of several power converters, sources, and loads. This implementation can be extended for use in microgrids. The switching functions allow seeing in the systems how the flow of the power is in a natural way so that the power balance does not require a very complex mathematical description that increases the hardware resources of a HIL.

Data Availability

The simulation data used to support the findings of this study are available from the corresponding author upon request.

Conflicts of Interest

The authors declare that they have no conflicts of interest.

Acknowledgments

The authors acknowledge to the Instituto Politécnico Nacional (IPN) Mexico, for its facilities where it has been possible to carry out this work, Comisión de Operación y Fomento de Actividades Académicas of the IPN (COFAA), for its financial support for the publication of this research article, and the Universidad Autonoma de Chihuahua (UACH) Mexico, for academic support granted for the realization of this research.

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Copyright © 2019 Marco Antonio Sánchez Vázquez et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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