Emulator Based on Switching Functions for a Dual Interleaved Buck-Boost Converter

Table 4

Comparison between different implementation strategies.

Implementation	Sampling Frequency	Number of steps per switching cycle	Multipliers	Resources FPGA; (CYCLONE 4 22K)
PWLM multiplier multiplexed in equation row	52.5 MHz	700	3	14.67%
PWLM multiplexer multiplexed in matrix row	105 MHz	1400	9	89.60%
SFM	150 MHz	2000	5	43.63%