Design Space Exploration for High-Speed Implementation of the MISTY1 Block Cipher

Table 5

FPGA implementation and comparison.

Ref.	Algorithm	Area (slices)	Speed (Gbps)	Freq (MHz)	Eff. (Mbps/slices)
[24]	AES	35,328	260	508	7.36
[25]	AES	4339	75.92	593	17.50
[23]	Camellia	2805	28.4	221.6	10.12
[20]^∗	MISTY1	1865	0.56	79	0.3
[20]^∗	MISTY1	4732	7.2	96	1.52
[20]^∗∗	MISTY1	2920	21.9	342	7.5
[20]^∗	MISTY1	4039	12.6	168	3.12
[20]^∗∗	MISTY1	2920	21.9	342	7.5
[21]^∗	MISTY1	1265	16.3	254.5	12.9
[22]^∗	MISTY1	6322	10.18	159	1.61
[22]^∗∗	MISTY1	2506	38.9	607.5	15.5
[22]^∗	MISTY1	6322	19.4	303	3.07
[22]^∗∗	MISTY1	2506	38.9	607.5	15.5
Ours	MISTY1	1509	43	673.8	28.5
	MISTY1	1331	25.2	393.7	18.9

^∗Results published in papers cited. ^∗∗Results obtained by authors with the implementation on the same FPGA.