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Multicriteria Deming Regressive African Buffalo Optimized Mapping for 3D NoC Architecture Design
Purpose. Networks-on-Chip (NoC) is a network-based communication between operating cores and intellectual property (IP) cores integrated on the same chip. An efficient design of NoC ensures high-speed data transfer and minimum essential connections in large-scale multicore, low power applications. Design/methodology/approach. A unique technique called Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory (MDRABOMWDGT) is introduced for an efficient Network-on-Chip architecture design. The main aim of the proposed technique is to find efficient operating cores integrated on the chip with minimum time. Initially, a set of IP cores are listed with their connections from the benchmark dataset. Then Multicriteria Deming Regressive African Buffalo Optimization is applied to the topology for mapping strategy on 3D NoC, with communication metrics such as throughput, latency, and computation time. The optimization technique initializes the population of cores in search space. For each core in the network, communication metrics are measured; then Deming regression is applied to analyze multicriteria functions for minimizing computation time. Further, fitness is measured to get an optimal IP core for improving the performance of mapping in 3D NoC. Findings. Comprehensive experimental evaluation is conducted using a benchmark dataset, communication metrics are measured, and results show significant improvement in performance with respect to energy parameters compared to state-of-the-art works. Originality/value. The mapping strategy for 3D NOC is developed and the results are compared with the state-of-the-art techniques.
Digital systems are constructed with a large number of cores on a single integrated circuit. Network-on-chips (NoCs) have emerged as a communication backbone for facilitating the high degree of integration in many-core chips. Placing multicores with several on-chip processing elements in one chip offers greater performance gains, but it faces many challenges. The key challenge is to offer efficient, low power, scalable, and reliable communication among these cores. Efficient 3D Networks-on-Chip (NoC) designs are required to improve the QoS-aware communication and low power demands of large-scale multicore applications.
With the continual technology development in VLSI, new integrated circuits (ICs) contain a large number of processing components on a single chip directing to communication deficiency and design complexity in the System-on-Chip. To handle this issue, a Network-on-Chip (NoC) has emerged as a novel model for providing efficient communication structural design. While considering the more intellectual property (IP) cores in the design of NoC, the performance of the system gets decreased. In such scenarios, flexibility and assurance are primary concerns for regular and irregular topologies. In general, the NoC regular and irregular topologies include certain limitations such as poor communication and higher network resource utilization. In addition, the area and performance are two significant factors in heterogeneous irregular networks. However, the design of these networks with low power consumption for large-scale multicore applications is more difficult. Therefore, the optimization of architectural design in the on-chip network is essential to maximize the performance of the network by minimizing resource utilization.
Three-dimensional Network-on-Chip (3D NoC) architecture is achieved for addressing the on-chip communication delay next generation System-on-Chip (SoC) systems. 3D NoC is designed to obtain better performance and lower power consumption. 3D NoC includes multiple planar layers and vertical communication. The vertical communication of 3D NoC is costly and complex to manufacture. In addition, 3D architecture takes low power and occupies more area per chip floorplan. Hence, more efficient architectures should be designed. Based on this motivation, the Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory (MDRABOMWDGT) technique is used for achieving an efficient 3D NoC design. The MDRABOM is designed with the implementation of the weighted directive graph theory and Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory.
1.1. Paper Outline
The rest of this paper is structured into five different sections. Section 2 reviews the related works. Section 3 provides a brief description of the MDRABOM technique for solving the multicriteria 3D NoC design problem. Experimental assessment of the proposed and the existing algorithm is described with benchmark dataset in Section 4; subsequently the performance analysis is provided in Section 5. At last, the conclusion and future work are presented in Section 6.
2. Related Works
A Stochastic Multiobjective Pareto-Optimization Framework was introduced in  for designing automatic Network-on-Chip to reduce network latencies and power utilization. But the designed framework was not efficient to improve the quality of automated NoC designs for multicore systems. A self-adaptive chicken swarm optimization algorithm (SCSO) was developed in  for efficient mapping to minimize the power consumption of NoC. However, the designed algorithm failed to consider 3D topologies, and mapping with other performance metrics like area, the delay was not considered.
A knowledge-based memetic algorithm (KBMA) was designed in  for 3D NoC mapping with standard network topologies. But the algorithm was not effective for application mapping by adopting different metaheuristics algorithms. Butterfly Fat Tree (BFT) topologies were developed in  for improving the power and performance analysis of 3D Network-on-Chip design. The designed method minimizes the network latency, but the higher throughput was not achieved. A deterministic and scalable arbitration mechanism was introduced in  to minimize the average latency. But the higher network throughput was not achieved.
Evaluation of Wireless Network-on-Chip architecture design was introduced in  for 3D wireless NoC design to initiate data communication with minimum energy consumption. However, pumping liquid through the microchannels can cause high pressure drops causing structural instability in the chip. An adaptive thermal-aware routing (ATAR) method was introduced in  to reduce the peak on-chip temperature. But the model failed to solve the problem of the thermal-aware solution in 3D many-core systems.
A multiobjective design space exploration framework was introduced in  for Network-on-Chip power grid design. But the framework failed to use an efficient evolutionary technique to minimize the convergence time. The machine learning techniques were introduced in  for designing the NoC architecture components. Though the designed technique minimizes the latency and time to get optimized solutions were not minimized. The Simulated Allocation (SAL) algorithm was designed in  to minimize the communication power and latency during the mapping process. However, the designed algorithm failed to consider the network throughput.
A genetic algorithm and Monte Carlo simulation techniques were introduced in  for improving the reliability and minimizing the energy consumption of embedded systems implemented with Network-on-Chip (NoC). The designed algorithm minimizes the computational runtime, but the performance of latency and throughput was not analyzed. A Butterfly Fat Tree (BFT) based design with a zone-based routing policy was introduced in  to minimize the latency and power consumption. But the method failed to involve the mapping process of IP cores with different layers.
A bat mapping algorithm (BMAP) was designed in  for mapping the IP cores. The designed algorithm minimizes the latency and power consumption. But the other metrics such as area and delay were not considered during the mapping process. A heuristic application mapping algorithm was designed in  for mesh-based NoC design to reduce both total energy and runtime. But the mapping algorithm was not applicable for 3D mesh NoC design.
A hybrid Scalable-Minimized-Butterfly-Fat-Tree (H-SMBFT) topology was introduced in  for on-chip communication. The designed topology minimizes the latency and energy consumption, but the throughput analysis was not performed. The different mapping approaches were developed in  for NoC design implementation. However, efficient heuristic algorithms were not considered for fast NoC designs to minimize the execution time of the mapping process.
Gaussian-based optical NoCs design was performed in  to ensure accurate and reliable communication on-chip. The designed method increases the throughput and minimizes the latency, but the computation time was not minimized. A hardware-efficient WiNoC with honeycomb topology was introduced in  for minimizing the resources such as network cost, delay, and energy utilization. However, this method failed to concentrate on delay and high power consumption.
Bat mapping algorithm was introduced in  for mapping on NoC strategy. But the algorithm failed to resolve the multiobjective problems during the mapping process. The EsyTest strategy was introduced in  to reduce the impact of test procedures on the Networks-on-Chip and to minimize the execution time. However, BIST causes significant performance loss due to data dependencies .
Machine learning algorithm-based applications have been deployed in  for supporting the Internet of things (IoT) and web search engines without losing accuracy in order to satisfy human requests. A new latency model was proposed in  for the routers which characterize the network contentions among different traffic flows from sharing of network resources.
A methodology was proposed in  to generate an NoC architecture along with a scheduling technique customized for different DNNs. However, crossbar-based in-memory computing may significantly increase the volume of on-chip communication since the weights and activations are on-chip. A new optimization technique called the African Buffalo Optimization was proposed in .
A detailed survey of the work is done in  in last decade in the domain of application mapping. An improvised cluster based mapping with metaheuristic search algorithm called simulated annealing with tabu search (SAT) was proposed in  to analyze and optimize the power consumption of NoC-based systems.
Liquid state machine (LSM) is an attractive spiking neural network (SNN) introduced in  for Network-on-Chip- (NoC-) based neuromorphic platforms due to their biological characteristics and hardware efficiency. But the randomly connected topology of the liquid in LSM brings different dataflow and communication congestion on the NoC-based platform. A new low complexity heuristic algorithm, CastNet, was designed in  for the application mapping and bandwidth constrained routing algorithm for mesh-based NoC architectures aiming to minimize the energy consumption. However, mapping applications represented by the weighted task graphs onto the mesh architectures is an NP-hard problem.
3. Proposed Methodology
The proposed technique is designed with the implementation of weighted directive graph theory and Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory. Figure 1 demonstrates the architecture of the proposed MDRABOM technique for 3D NoC architecture design. Initially, the numbers of IP cores are collected from the benchmark dataset. Intellectual property (IP) core also known as IP block is a reusable part of a cell or integrated circuit (IC) design. To design the integrated circuit for improving the performance of the system, the optimized cores are used. In order to examine the different metrics and choose the optimal cores based on the multicriteria optimization technique, Deming regression is used. The mapping is carried based on the multiple objective functions such as energy consumption, area, power, and delay to find the optimal IP core. This helps to achieve the energy and power-aware architecture design.
The proposed technique is designed with the implementation of Multicriteria Deming Regressive African Buffalo Optimized Mapping Weighted Directive Graph Theory.
3.1. Key Contributions of the Proposed MDRABOM
Some of the key technical contributions of the MDRABOM are listed as follows.(1)To improve the network throughput and latency, weighted directive graph theory is applied for NoC mapping. The mapping is performed based on the Deming Regressive African Buffalo Optimization technique to find the power and energy-efficient IP core from the population. The lesser number of cores in the graph minimizes the route length. This improves the transmission of the packet towards the destination and minimizes the latency.(2)To minimize the computation time, a Deming regression is applied to an African Buffalo Optimization technique and fitness measure based on multicriteria function such as energy consumption, power, delay, and area. The regression analysis in the optimization technique finds the optimal IP core for 3D NoC design with minimum time.(3)Finally, extensive simulations are carried out using a benchmark dataset to evaluate the performance of the MDRABOM technique and other optimization works. The obtained result shows that the MDRABOM technique is highly efficient compared to the other methods.
3.2. Network Model
The proposed MDRABOM technique uses the weighted directive graph for NoC mapping. The weighted directed graph-based mapping is a mathematical model used to determine the relationship between the two variables.
From Figure 2 a weighted undirected graph where ‘’ denotes the number of vertices (i.e., cores); ‘’ stands for the links between the nodes. Figure 2 demonstrates the undirected weighted directive graph with five vertices (i.e., nodes) and seven edges (i.e., links). For each node in the network , we have to find the multicriteria (i.e., multiobjective) functions such as energy consumption, area, power, and delay for mapping. The node with the best fitness has a higher weight than the others in the graph. The mapping is performed by applying the injective map function in the graph theory using the following mathematical formula:where denotes a mapping function, and , denote a node in the network. The optimized resources are determined for applying multiobjective optimization of every node. Energy consumption of resources is , area , power , and delay of node (). By satisfying equation (2), optimal node selection is performed. In order to find neighboring node (i.e., minimum distance) and links, binary mapping has been applied.where symbolizes mapping probability function among nodes. If mapping function returns ‘1’, then optimal node is detected. Otherwise, mapping function returns ‘0’. In following sections, mathematical model of Multicriteria Deming Regressive African Buffalo Optimization is discussed.
3.3. Multicriteria Deming Regressive African Buffalo Optimization Model
In order to find the optimal node, Multicriteria Deming Regressive African Buffalo Optimization model is applied. The African Buffalo Optimization is a metaheuristic algorithm to identify the position of the best buffalo from the population. The proposed optimization was inspired by the behavior of buffalos in the African forests. The proposed optimization was inspired by the behavior of buffalos in the African forests. On the contrary to existing African Buffalo Optimization, the proposed MDRABOMWDGT technique uses multicriteria optimization and Deming regressive function. The multicriteria optimization considers the many objective functions, namely, energy consumption (), area (), power (), and delay (). Deming regression function is applied into an optimization technique to analyze the estimated factors such as energy consumption (), area (), power (), and delay () of each IP core.
Randomly initialize the population of the IP cores (i.e., buffalos) in search space. For each IP core, the multiple objective functions are measured for evaluating the fitness. The multicriteria work is applied for identifying and comparing the different policy options by calculating their effects, performance, and impacts . The multicriteria work provides a systematic approach for supporting complex decisions based on the predetermined criteria and objectives. After that, Deming regression function is utilized for examining the multiple objective functions. If the fitness of one buffalo is greater than the other, the position of buffalos’ gets updated, and it finds the optimal. This process is repeated until the maximum iteration is reached. The optimization is more robust and efficient than the other optimization algorithm since it uses a few learning parameters resulting in guaranteeing the fast convergence rate. Therefore, the initialization process is expressed as follows:where denotes IP cores. After the initialization in search space, the fitness is computed based on multiple objective functions of energy consumption (), area (), power (), and delay ().
Initially, the energy consumption is calculated as given below:
From (4), indicates energy consumed by module ‘’, and ‘’ represents the temperature rise at module ‘’ with respect to transfer resistance at module ‘’.
Area () is defined as a total area model; 3D NoC is a sum of router/switch area (), area of intellectual property (IP) cores (), and area of on-chip global interconnects (). The area is formulated as given below:where denotes the number of planes presented in 3D NoC, denotes the number of switches in the 2D or 3D network, and denotes the area of switch . From (5), area of on-chip global interconnection ‘’ is measured as follows:where denotes the number of links presented in the 3D networks, represents flit size in bits, denotes a wire width, indicates a spacing between wires, and denotes a wire length of the global interconnection in the on-chip network.
Power () is considered as a global link power which is the sum of the three different power consumptions of 3DNoC. The global link power is estimated as given below:where denotes a global link power, denotes a power due to circuit switching, denotes a short circuit power, and denotes a static power.
Delay () is measured based on three factors as a router, propagation delay due to link or channel, and serialization of packets. The overall delay is measured as given below:where denotes an average hop count, denotes a router, denotes a propagation delay due to link or channel, and indicates a serialization of packets. The Deming regression function is applied into an optimization technique to analyze the estimated factors such as energy consumption (), area (), power (), and delay () of each IP core. Deming regression is a machine learning technique to analyze the given input variables and find the best fit from the populations. The regression analysis is performed as given below:where denotes an output of multiobjective estimation of cores , and indicates the regression coefficients, and denotes multiobjective estimation of the cores, i.e., energy consumption (), area (), power (), and delay (). Based on the regression analysis, the node that has minimum energy consumption, area utilization, power consumption, and delay is chosen as the optimal from the population. After the analysis, the fitness is measured to find the best-fit IP core.where denotes a fitness function, and denotes an argument of a minimum function. Based on the fitness value, the two processes such as exploration and exploitation are performed as given below:where indicates an updated buffalos’ exploitation of the ‘’ th buffalo, denotes a current position of the ’ th buffalo, indicates an exploration of the buffalos’, and are the learning parameters set values from 0.1 to 0.6, indicates the best fitness of buffalo’s, and refers to the individual buffalo’s best location. After that, the location of buffalos is updated as given below:
From (13), indicates an updated location of buffalos, and denotes a parameter value set as 0.5. If the convergence is not met, then go back to update buffalos; otherwise, stop the process.
Figure 3 illustrates the flow process of Multicriteria Deming Regressive African Buffalo Optimization for finding the optimal IP core. After finding the IP core, the mapping probability is done using equation (2) with the help of the injective mapping function. If the mapping function value is ‘1’, then the optimal node is identified. Otherwise, the mapping function returns ‘0’. The entire process gets iterated until the maximum iteration is reached. As a result, the optimized neighboring core is selected for direct communication on 3D NoC.
The algorithmic process of the proposed MDRABOM technique is described as follows.
Algorithm 1 describes the step-by-step process of Multiobjective Deming Regressive African Buffalo Optimized Mapping to improve the efficiency of 3D NoC architecture design. Initially, the populations of IP cores are initialized in search space. After the initialization, the multicriteria function is measured for each IP core in the population. Then the Deming regression function is applied to analyze the multicriteria function. After the analysis, the optimal one is selected through the fitness measure. If the fitness of the current core, i.e., , is greater than the other , the position of the ‘’ th buffalo gets updated. Finally, the current best core is identified and mapped using the graphical model. This process gets repeated until it reaches the maximum iteration. After that, the mapping is performed based on the probability. In this way, an efficient mapping of cores in the 3D NoC architecture is performed with minimum time.
4. Experimental Settings
Experimental evaluation of proposed MDRABOM technique and two existing methods, namely, Stochastic Multiobjective Pareto-Optimization Framework  and SCSO  are implemented in Python. The algorithm processes are written by C++ code, and it is implemented in Python. In order to conduct the experiment, the MCNC Benchmark Netlists dataset is used . The MCNC Benchmark Netlists are often used to perform the 3D Network-on-Chip architectures design. The benchmark circuits are in Yet Another Language (YAL) format. For the experimental consideration, the IP cores are taken from the benchmark dataset. The circuit description of the MCNC Benchmark dataset is given in Table 1.
5. Performance Results and Discussions
The performance discussion of the proposed MDRABOM technique and two existing methods, namely, Stochastic Multiobjective Pareto-Optimization Framework  and SCSO , are carried out with different parameters such as throughput, latency, and computation time. The performance results of the various parameters are discussed with help of a table and graphical representation.
5.1. Impact of Throughput
Throughput is the actual rate that the information (i.e., packets) is transferred between source-destination pairs in NoC. It also helps to perform the communication between the IP cores or blocks. The formula for calculating the throughput is given below:where denotes a throughput, and is measured in terms of cycles. Therefore, the overall throughput is measured in the unit of the packets/cycles/IP block.
Table 2 describes the comparison of throughput for 5 different circuits, namely, Apte, ami33, ami49, Xerox, and hp taken from the MCNC Benchmark Netlists. The above table provides the performance of throughput using three different techniques, namely, MDRABOMWDG, Stochastic Multiobjective Pareto-Optimization Framework , and SCSO .
The observed results show that the proposed MDRABOMWDG offers higher performance when compared to existing methods. Let us consider the Apte circuit with 9 IP cores. The throughput of the MDRABOMWDG is 0.74 packets/cycles/IP block.
The proposed MDRABOMWDG has obtained average percentage improvement for above circuits in throughput by 3.8% and 7% compared to SMPOF and SCSO, respectively.
The throughput of the conventional methods Stochastic Multiobjective Pareto-Optimization Framework  and SCSO  is 0.72 packets/cycles/IP block and 0.7 packets/cycles/IP block, respectively. The throughput is measured according to the packet injection rate. The packet injection rate is measured in terms of packets/cycles/IP block. Figure 4 shows the performance analysis of throughput for three different techniques, namely, MDRABOMWDG, Stochastic Multiobjective Pareto-Optimization Framework , and SCSO . From the graphical representation, the throughput is measured for different circuits. The graphical plot indicates that the throughput of the MDRABOMWDG technique is higher than the other existing methods. The reason behind this improvement is to find the resource-optimized IP cores using the Multicriteria Deming Regressive African Buffalo Optimized Mapping technique. The resource-efficient IP cores are selected based on the multicriteria optimization technique such as energy consumption, area, power, and delay. The selected IP cores increase the packet transmission. Besides, the reduced number of average hop counts between source-destination pairs also improves the transmission by applying the weighted directive graph theory-based mapping.
5.2. Impact of Latency
The latency is referred to the average time taken to transmit the packets between source-destination pairs in NoC. Therefore, the latency is expressed as follows:where denotes a latency, and indicates an average time. The latency is measured in terms of clock cycles.
Table 3 reports the performance analysis of latency value for 5 various circuits, such as Apte, ami33, ami49, Xerox, and hp. The table provides the latency value of three different methods as proposed MDRABOMWDG, Stochastic Multiobjective Pareto-Optimization Framework , and SCSO . The latency of the data transfer using the proposed MDRABOM technique is minimized compared to existing techniques.
As shown in Table 3, the latency of the MDRABOMWDG technique is minimized when compared to other existing methods. This is due to the MDRABOMWDG technique that uses the weighted directive graph for NoC mapping. The mapping is done based on the Deming Regressive African Buffalo Optimization technique to find the optimal IP core for direct connection in the NoC design as shown in Figure 5. The lesser number of nodes in the weighted directive graph reduces the route length. This directs the transmission of the packet towards the destination with minimum latency. The proposed MDRABOMWDG has obtained average reduction in latency for above circuits by 12 and 24 clock cycles compared to SMPOF and SCSO, respectively.
5.3. Impact of Computation Time
The computation time is defined as the amount of time consumed by the algorithm to find the optimal core for efficient 3D NoC architectural design based on multiple objective functions. Therefore, the overall computation time is formulated as given below: indicates a computation time. The computation time is measured in milliseconds (ms).
Table 4 reveals the performance results of the computation time for identifying the resource-optimized IP cores with respect to the number of circuits taken from the benchmark dataset. The observed results indicate that the proposed MDRABOMWDG technique offers improved performance against the other two related approaches. This is proved through statistical analysis.
The experiment is conducted with Apte circuit and 9 IP cores, MDRABOMWDG technique has taken the of time to find the optimized core for 3D NoC design and the computation time of Stochastic Multiobjective Pareto-Optimization Framework  and SCSO  is observed to be and for finding the optimal IP core. Similarly, the other circuits are considered with different counts of IP core to conduct the experiment. Totally five runs are observed for each method with different counts of input IP cores as shown in Figure 6.
The computation time gets increased while increasing the number of cores taken as input. But comparatively, the proposed MDRABOMWDG technique minimizes the computation time. The appropriate reason is that the Multicriteria African Buffalo Optimization technique uses the Deming regression to analyze the multiple objective functions of each IP core. Based on the regression, the fitness is measured and identifies the best-fitted IP core with minimum time for 3D NoC design. The proposed MDRABOMWDG has obtained average reduction in computation time for above circuits by 3 and 5.2 ms compared to SMPOF and SCSO, respectively.
6. Conclusion and Future Work
In this paper, a novel MDRABOMWDG technique-based mapping approach was developed for 3D NoC design. The efficiency of the mapping approach is improved based on the multiple objective functions. The MDRABOMWDG technique is developed by the integration of a graph theory-based Multicriteria African Buffalo Optimization technique. Here multicriteria optimization problem is solved and performing the efficient IP core mapping on-chip that improves the throughput and reduces the latency of data communication. The optimization technique uses the Deming regression to analyze the various metrics and select the optimal cores from the population. This process helps to minimize the computation time of core mapping. The experimental evaluations are conducted to estimate the performance of the MDRABOMWDG technique over the two existing optimization methods. The experimental outcome illustrates that the MDRABOMWDG technique produces improved performance in minimization of latency and computation time and increases the throughput compared to the conventional methods.
6.2. Future Work
In future work we are planning to use Booksim 2.0 and Python simulator for energy parameters calculation and use evolutionary multiobjective optimization techniques for mapping both (regular and irregular) topologies, thereby achieving better results compared to the state-of-the-art methods.
The required data can be obtained from the corresponding author upon request.
Conflicts of Interest
The authors declare that they have no conflicts of interest.
Editing and writing were supported by Debre Tabor University, Ethiopia.
R. ShamimN. Singh and R. S Narde Gonzalez-Hernandez, J.V Ganguly, S.G Venkatarman, and S. G. Kandlikar, “Evaluation of wireless network-on-chip architectures with microchannel-based cooling in 3D multicore chips,” Sustainable Computing: Informatics and Systems, Elsevier, vol. 21, pp. 165–178, March 2019.View at: Publisher Site | Google Scholar
N. A. Kumar, G. Shyni, G. Peter, A. A. Stonier, and V. Ganji, “Architecture of network-on-chip (NoC) for secure data routing using 4-H function of improved TACIT security algorithm,” Wireless Communications and Mobile Computing, Article ID 4737569, 9 pages, 2022.View at: Publisher Site | Google Scholar
J. Wang and M. EbrahimiL. Huang, X. Xie, Q. Li, G. Li, and A. Jantsch, “Efficient design-for-test approach for networks-on-chip,” IEEE Transactions on Computers, Volume68, Issue, vol. 2, p. 198, 2019.View at: Google Scholar
Y. Seyedeh, H. Mirmahaleh, and A. Masoud Rahmani, “DNN pruning and mapping on NoC-Based communication infrastructure,” Microelectronics Journal, vol. 94, 2019.View at: Google Scholar
J. Beneoluchi Odili, M. N. Mohmad Kahar, and S. Anwar, “African buffalo optimization: a swarm-intelligence technique,” Procedia Computer Science, vol. 76, pp. 443–448, 2015.View at: Google Scholar
S. Li, S. Tian, Z. Kang et al., “A multi-objective LSM/NoC architecture co-design framework,” Journal of Systems Architecture, vol. 116, 2021.View at: Google Scholar
A. K. Loganathan, A. Alexander Stonier, Y. Uma Maheswari, G. Peter, and T. Samraj Lawrence, “A real-time implementation of air audit system for compressors towards energy conservation: an industrial case study,” Mathematical Problems in Engineering, vol. 2022, pp. 1–12, 2022.View at: Publisher Site | Google Scholar