Supplementary High-Input Impedance Voltage-Mode Universal Biquadratic Filter Using DVCCs

Abstract

To further extend the existing knowledge on voltage-mode universal biquadratic filter, in this paper, a new biquadratic filter circuit with single input and multiple outputs is proposed, employing three differential voltage current conveyors (DVCCs), three resistors, and two grounded capacitors. The proposed circuit realizes all the standard filter functions, that is, high-pass, band-pass, low-pass, notch, and all-pass filters simultaneously. The circuit enjoys the feature of high-input impedance, orthogonal control of resonance angular frequency (𝜔_o), and quality factor (Q) via grounded resistor and the use of grounded capacitors which is ideal for IC implementation.

1. Introduction

Analog filters are the basic building blocks and widely used for continuous-time signal processing. Application of analog filters employing current-mode active elements extends over a large number of fields [1]. The filter circuits may be used in phase-locked loop frequency modulation stereo demodulators, touch-tone telephone tone decoder, and cross-over networks in a three-way high fidelity loudspeaker [2, 3]. In the literature several voltage-mode biquadratic filters are presented which uses different types of current conveyors [4–28]. The voltage-mode filters with high-input impedance are of great interest because they can be easily cascaded to synthesize higher-order filters [7, 10, 13, 17, 26, 28]. In the literature there are a number of voltage-mode universal biquadratic filters with single-input multiple-outputs (SIMO) [4–12, 18] that are available. However, these reported circuits suffer from one or more of the following drawbacks:(i)excessive use of passive components [4, 6, 7];(ii)low-input impedance [5, 6, 8, 9, 11, 18];(iii)lack of orthogonal control over the resonance angular frequency (𝜔_𝑜) and quality factor (Q) [10, 12].

In this paper, a new voltage-mode universal biquadratic filter using three differential voltage current conveyors [29], two grounded capacitors, and three resistors is presented. The circuit realizes the entire standard filter functions, that is, high pass (HP), band pass (BP), low pass (LP), notch (NH), and all pass (AP) from the same circuit configuration. The circuit also possesses high-input impedance and provides orthogonal control of the 𝜔_𝑜 and Q via grounded resistor.

2. Differential Voltage Current Conveyor(DVCC)

The DVCC is first introduced long back as a modified current conveyor by Pal [30] and developed by Elwan and Soliman in 1997 [29]. It is a versatile building block, especially designed to handle differential and floating input signals [30, 31]. Using standard notation, the terminal relations of a DVCC are shown in Figure 1 and described by the following matrix equation: ⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣𝐼_𝑌1𝐼_𝑌2𝑉_𝑋𝐼_𝑍+𝐼_𝑍−⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦=⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣00100−00001−000110000000000⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣𝑉_𝑌1𝑉_𝑌2𝐼_𝑋𝑉_𝑍+𝑉_𝑍−⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦.(1)

(a)

(b)

Figure 1 

(a) Symbol of DVCC. (b) CMOS implementation of DVCC.

The difference of the 𝑌₁ and 𝑌₂ terminal voltages is conveyed to the X terminal; the current input at the X terminal is conveyed to the Z+, with the same polarity and Z− terminal with inverse polarity. The DVCC is characterized by high-input impedance at the 𝑌₁ and 𝑌₂ terminals, high-output impedance at the Z+ and Z− terminals, and low impedance at the 𝑋 terminal.

3. Proposed Circuit

The proposed voltage-mode universal biquadratic filter is shown in Figure 2, employing three DVCCs, three resistors, and two grounded capacitors. The routine analysis of the proposed circuit in Figure 2 using (1) yields the filter transfer functions as 𝑉_OUT1𝑉_IN=1𝑉𝑠²𝐶₁𝐶₂𝑅₁𝑅₂+𝑠𝐶₁𝑅₃+1_OUT2𝑉_IN=𝑠²𝐶₁𝐶₂𝑅₁𝑅₂𝑉𝑠²𝐶₁𝐶₂𝑅₁𝑅₂+𝑠𝐶₁𝑅₃+1_OUT3𝑉_IN=𝑠𝐶¹𝑅₁𝑉𝑠²𝐶₁𝐶₂𝑅₁𝑅₂+𝑠𝐶₁𝑅₃+1_OUT4𝑉_IN=𝑠²𝐶₁𝐶₂𝑅₁𝑅₂+1𝑉𝑠²𝐶₁𝐶₂𝑅₁𝑅₂+𝑠𝐶₁𝑅₃+1_OUT5𝑉_IN=𝑠²𝐶₁𝐶₂𝑅₁𝑅₂−𝑠𝐶₁𝑅₁+1𝑠²𝐶₁𝐶₂𝑅₁𝑅₂+𝑠𝐶₁𝑅₃+1.(2) It can be seen from (2) that an LP response is obtained from 𝑉_OUT1; HP response is obtained from 𝑉_OUT2; BP response is obtained from 𝑉_OUT3; NH response is obtained from 𝑉_OUT4; if 𝑅₃ = 𝑅₁, AP response is obtained from 𝑉_OUT5. In all the cases, the parameters 𝜔_𝑜 and Q of the filter can be found as 𝜔_o=1𝐶₁𝐶₂𝑅₁𝑅₂^1/2𝑄=1,𝑅₃𝑅₁𝑅₂𝐶₂𝐶₁.(3) From (3), the Q of the proposed filter can be controlled independently of 𝜔_𝑜 by varying 𝑅₃. Since the input voltage signal is connected directly to the 𝑌₁ port of the DVCC (1) and the input current to the 𝑌₁ port is zero (𝐼_𝑌1 = 0), the circuit has the feature of high-input impedance. Thus the proposed circuit is capable to realize all five standard filter functions simultaneously and without changing the circuit topology, unlike the previously proposed circuit in [26]. The circuit reported in [26] uses two floating resistors but the proposed circuit employs only one floating resistor. The circuit needs no component-matching conditions except for the all-pass filter realization.

Figure 2 

Voltage-mode universal biquadratic filter.

Note that the proposed circuit uses two grounded capacitors at the 𝑍-terminal and three resistors at the 𝑋-terminal of the DVCCs. The design offers the feature of a direct incorporation of the shunt parasitic capacitances at the 𝑍-terminals and the series parasitic resistances at the 𝑋-terminal, as a part of the main capacitors (𝐶₁ and 𝐶₂) and resistors (𝑅₁, 𝑅₂, and 𝑅₃).

4. Nonideal Analysis

Taking the nonidealities of the DVCC into account, the relationship of the terminal voltages and currents of the DVCC can be rewritten as ⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣𝐼_𝑌1𝐼_𝑌2𝑉_𝑋𝐼_𝑍+𝐼_𝑍−⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦=⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣𝛽0000000000_𝑘10−𝛽0_𝑘2𝛼0_𝑘10000−𝛼_𝑘20000⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣𝑉^𝑌1𝑉_𝑌2𝐼_𝑋𝑉_𝑍+𝑉_𝑍−⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦,(4) where 𝛽_𝑘1(𝑠), 𝛽_𝑘2(𝑠) represent the frequency transfers of the internal voltage followers and 𝛼_𝑘1(𝑠), 𝛼_𝑘2(𝑠) represent the frequency transfers of the internal current followers of the kth-DVCC, respectively. They can be approximated by first-order low-pass functions, which can be considered to have a unity value for frequencies [30]. If this circuit is working at frequencies much less than the corner frequencies of 𝛽_𝑘1(𝑠), 𝛽_𝑘2(𝑠), 𝛼_𝑘1(𝑠), and, 𝛼_𝑘2(𝑠), namely, then 𝛽_𝑘1(𝑠) = 𝛽_𝑘1=1−𝜀_𝑘𝑣1 and 𝜀_𝑘𝑣1(|𝜀_𝑘𝑣1≪1|) denotes the voltage tracking error from the 𝑌₁ terminal to the 𝑋 terminal of the kth-DVCC; 𝛽_𝑘2(𝑠)=𝛽_𝑘2=1−𝜀_𝑘𝑣2 and 𝜀_𝑘𝑣2(|𝜀_𝑘𝑣2≪1|) denotes the voltage tracking error from the 𝑌₂ terminal to the 𝑋 terminal of the kth-DVCC, 𝛼_𝑘1(𝑠)=𝛼_𝑘1=1−𝜀_𝑘𝑖1, and 𝜀_𝑘𝑖1(|𝜀_𝑘𝑖1≪1|) denotes the current tracking error from the 𝑋 terminal to the 𝑍+ terminal; 𝛼_𝑘2(𝑠)=𝛼_𝑘2=1−𝜀_𝑘𝑖2 and 𝜀_𝑘𝑖2(|𝜀_𝑘𝑖2≪1|) denotes the current tracking error from the 𝑋 terminal to the 𝑍− terminal of the kth-DVCC.

Taking the tracking errors of the nonideal DVCC into account, the denominator of (2) becomes 𝐷(s)=+𝑠₂𝑠𝐶𝐶₁₁𝐶₂𝑅₂𝛼₂₂𝑅₃𝛼₁₁+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁𝑅₃𝛽₂₂𝛽₃₁𝛼₁₁𝛼₂₂+𝛽₁₂𝛽₂₂𝛽₃₂.(5) The parameters 𝜔_𝑜 and Q from (5) can be rewritten as 𝜔_𝑜=𝛽¹²𝛽₂₂𝛽₃₂𝐶₁𝐶₂𝑅₂𝛼₂₂𝑅₃𝛼₁₁+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁^1/2𝑄=1,𝑅₃𝛽₃₁𝛼₁₁𝐶²𝑅₂𝛽₁₂𝛽₃₂𝑅₃𝛼₁₁+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁𝐶₁𝛽₂₂𝛼₂₂^1/2.(6) The active and passive sensitivities of the proposed SIMO voltage-mode filter are derived from (6). These are as follows: 𝑆^𝜔𝑜_{𝐶1,𝐶2,𝑅2}=−1𝑆_{𝜔𝑜𝑅1}2,=−12𝑅¹𝛽₁₂𝑆𝑅₃𝛼_{11𝜔𝑜𝛽22,𝛽32}+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁,=−𝑆^𝜔𝑜_𝛼22=1𝑆_{𝜔𝑜𝛽12}2,=12𝑅³𝛼₁₁−𝑅₃𝛼₁₁𝛽₂₁𝑆_{𝜔𝑜𝑅3,𝛼11}𝑅₃𝛼₁₁+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁,=−12𝑅³𝛼₁₁1−𝛽₂₁𝑆_{𝜔𝑜𝛽21}𝑅₃𝛼₁₁+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁,=12𝑅³𝛼₁₁𝛽₂₁𝑆_{𝑄𝐶2,𝑅2}𝑅₃𝛼₁₁+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁,=−𝑆^𝑄𝐶₁=12,𝑆^𝑄𝛽32=−𝑆^𝑄𝛽_22,𝛼22=1𝑆_𝑄𝑅12,=12𝑅¹𝛽₁₂𝑆_{𝑄𝑅3,𝛼11}𝑅₃𝛼₁₁1−𝛽₂₁+𝑅₁𝛽₁₂,=−2𝑅¹𝛽₁₂−𝑅₃𝛼₁₁1−𝛽₂₁2𝑅𝑆₃𝛼_11𝑄𝛽311−𝛽₂₁+𝑅₁𝛽₁₂,𝑆=−1,_𝑄𝛽12=12𝑅³𝛼₁₁+2𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁𝑆_𝑄𝛽21𝑅₃𝛼₁₁+𝑅₁𝛽₁₂−𝑅₃𝛼₁₁𝛽₂₁,=−12𝑅³𝛼₁₁𝛽₂₁𝑅₃𝛼₁₁1−𝛽₂₁+𝑅₁𝛽₁₂.(7) From the results it is evident that the sensitivities are low and within unity in absolute value. Thus the proposed circuit can be classified as insensitive as all the active and passive sensitivities are less than or equal to unity [28].

5. Simulation Results

The performance of the proposed voltage-mode universal biquadratic filter in Figure 2 is verified using the PSPICE simulation program. The MOS transistors are simulated using 0.35 μm CMOS process parameters given in Table 1. The aspect ratios of the transistors used in the simulation are given in Table 2. The supply voltages and biasing voltage are given by 𝑉+=2V, 𝑉−=−1.9V, 𝑉_𝑏1=−1.23 V, and 𝑉_𝑏2=−1.15 V, respectively. The proposed circuit is designed for 3.18 MHz and Q = 1 by choosing 𝑅₁=𝑅₂=𝑅₃=5 kΩ and 𝐶₁=𝐶₂=10 pF. Figure 3 shows the simulated gain responses for the LP, HP, and BP filters and agrees well with the designed values. Figures 4 and 5 show the simulated gain and phase responses for the NH and AP filters. Next, Q tuning of BP filter at constant frequency of 3.18 MHz is shown in Figure 6. The circuit of Figure 2 is designed for Q values of 1, 5, and 10 with 𝑅₃ values as 5 kΩ, 1 kΩ, and 500 Ω, respectively, with 𝐶₁=𝐶₂=10 pF and 𝑅₁=𝑅₂=5 kΩ.

Table 1 

TSMC 0.35 μm CMOS process parameters.

Table 2 

Aspect ratios of the MOS in Figure 1.

Figure 3 

Gain plots of LP, HP, and BP filters for Q = 1 at 3.18 MHz.

Figure 4 

Gain and phase plots of NH filter for Q = 1 at 3.18 MHz.

Figure 5 

Gain and phase plots of AP filter for Q = 1 at 3.18 MHz.

Figure 6 

Q tuning (Q = 1, 5, and 10) of BP filter at 3.18 MHz.

To test the input dynamic range of the proposed filter, the simulation of the HP filter as example has been repeated for a sinusoidal input signal at 3.18 MHz. Figure 7 shows the input dynamic range of the HP filter which extends upto amplitude 200 mV (peak to peak) without significant distortion. In Figure 8, the total harmonic distortion (THD) of the 𝑉_OUT2 output voltage is given at 3.18 MHz operation frequency. Figure 9 shows the INOISE and ONOISE simulated amplitude-frequency responses of the proposed LP filter at 𝑉_OUT1.

(a)

(b)

Figure 7 

Input (a) and HP output (b) signal waveforms to demonstrate the ac dynamic range at 𝑉OUT2.

Figure 8 

THD variation with 𝑉IN for HP filter at 𝑉OUT2.

Figure 9 

The input and output referred noise spectral densities of the proposed LP filter at 𝑉OUT1.

6. Conclusion

The voltage-mode universal biquadratic filter realizes all the standard filter functions by employing three DVCCs and five passive components. It offers high-input impedance, which permit the use of circuits in cascade without requiring any impedance-matching device. Moreover, the proposed circuit enjoys the following features: orthogonal control of 𝜔_𝑜 and Q, low active and passive sensitivity, and the direct incorporation of parasitic resistance and parasitic capacitance at the X-terminal and Z-terminal of the respective DVCCs, as a part of main resistor and capacitor. So, the new circuit will enhance the existing knowledge on the voltage-mode universal biquadratic filter. PSPICE simulations with TSMC 0.35 μm process confirm the theoretical prediction.