Optimal ILP-Based Approach for Gate Location Assignment and Scheduling in Quantum Circuits

Table 4

The latency of the benchmark circuits achieved by the proposed approach compared with [8, 23].

Benchmark	Latency (𝜇s)			Improvement (%)
	The proposed model	GLC [8]	Yazdani et al. [23]	Over GLC [8]	Over Yazdani et al. [23]
[6-0-2]	14	38	23	63.15	39.13
[6-2-2]	76	121	121	37.19	37.19
[5-1-3]	152	191	239	20.41	36.40
[7-1-3]	155	205	263	24.39	41.06
[9-1-3]	142	170	383	16.47	62.92
[9-3-2]	192	202	259	4.95	25.86
[11-1-5]	595	677	659	12.11	9.71
Average				25.5	36.1