Adaptive Neuromorphic Circuit for Stereoscopic Disparity Using Ocular Dominance Map

Table 1

Model proposed	Hardware type	Method	Adaptability	Bioinspiration	Disparity range	Resolution	Power consumption
Shi and Tsang, 2003 [18]	Mixed analog & digital (use Gabor filter chips, AER Protocol, and Xilinx CPLD	Binocular energy model	Nonadaptive	Emulates disparity tuned complex cells	3 disparities	Low level vision	—
Díaz et al., 2007 [13]	Digital (use Gabors, FPGA based SOC that can be used in embedded systems)	Modified phase based technique	Adaptive (in the sense that it can dynamically adjust number of disparities)	Takes multiple disparity (estimates and integrates the results to emulate computations by many neurons in parallel)	FPGA can be configured to have flexible disparities depending on image, max (−24 to 24)	Subpixel resolution	—
Shimonomura et al., 2008 [19]	Mixed analog & digital (use aVLSI silicon retinas, Gabor chips to represent simple cells, & FPGA to compute disparity)	Energy model	Nonadaptive	Inspired by the hierarchical organization of simple and complex cell	5 disparities	Low level vision	225 mW
Mandal et al., 2010 [20]	Mixed analog & digital (use massively parallel SIMD Current-Mode Analog Matrix Processor and FPGA based microcontroller)	Binocular energy model	Nonadaptive	Bioinspired because it uses binocular energy model	3 disparities	Low level vision	250 mW
Rogister et al., 2012 [21]	Digital & software (use AER silicon retina for input and the rest of processing is done in software)	—	Nonadaptive	Inspired by the asynchronous event based dynamics of the brain	—	Low level vision	—
Our model	Pure analog, based on floating gate MOSFETs (uses ts-WTA as building block)	Position shift	Adaptive (the cell can learn any disparity during learning phase)	Takes inspiration from local, hierarchical processing, cortical plasticity, and columnar architecture of the brain	3 disparities but extendable to more disparities	Low level vision	180 mW (during learning phase) 60 mW (during detection phase)