Utilizing the Double-Precision Floating-Point Computing Power of GPUs for RSA Acceleration

<table class="table-group" id="tab4"><tr><td><table class="table"><tr><td class="thead-hr" colspan="4"><hr/></td></tr><tr><td class="align_left"><svg height="6.1673pt" id="M105" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 6.6501 6.1673" width="6.6501pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M495 86L479 114C446 82 419 66 409 66C401 66 401 72 406 97C420 166 436 231 453 297C489 435 454 448 428 448C406 448 384 439 354 422C305 394 222 327 161 247H159L183 345C200 415 194 448 173 448C143 448 82 410 23 351L38 325C64 349 95 371 105 371C111 371 116 365 109 336L25 -4L31 -12C50 -4 77 3 107 9C119 69 132 122 145 168C197 254 321 381 370 381C387 381 393 374 378 305L329 95C309 17 320 -12 345 -12C372 -12 430 19 495 86Z" id="g113-111"></path></g></svg> length (bit)</td><td class="align_center"> 1024</td><td class="align_center"> 1536</td><td class="align_center"> 2048</td></tr><tr><td class="align_left"><svg height="6.1673pt" id="M106" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 9.39034 6.1673" width="9.39034pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M689 332C689 394 670 448 646 448C620 448 597 421 597 396C597 386 600 381 608 372C619 359 620 334 620 315C620 150 538 45 454 45C414 45 386 67 386 122C386 138 388 158 394 180L457 426L452 432L377 416L315 156C302 100 259 45 216 45C176 45 148 67 148 122C148 133 152 158 156 180C162 212 173 259 194 332C201 357 206 384 206 405C206 430 198 448 174 448C125 448 66 406 23 342L43 319C84 368 110 383 121 383C126 383 128 382 128 377C128 370 127 359 122 343C99 268 84 204 77 156C74 137 70 111 70 104C70 25 125 -12 180 -12C228 -12 276 12 319 50C338 8 378 -12 418 -12C549 -12 689 166 689 332Z" id="g113-120"></path></g></svg> length (bit)</td><td class="align_center"> 23</td><td class="align_center"> 22</td><td class="align_center"> 22</td></tr><tr class="table-tr"><td colspan="4"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Maximal <svg height="6.1673pt" id="M104" style="vertical-align:-0.2063904pt" version="1.1" viewbox="-0.0498162 -5.96091 9.39034 6.1673" width="9.39034pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M689 332C689 394 670 448 646 448C620 448 597 421 597 396C597 386 600 381 608 372C619 359 620 334 620 315C620 150 538 45 454 45C414 45 386 67 386 122C386 138 388 158 394 180L457 426L452 432L377 416L315 156C302 100 259 45 216 45C176 45 148 67 148 122C148 133 152 158 156 180C162 212 173 259 194 332C201 357 206 384 206 405C206 430 198 448 174 448C125 448 66 406 23 342L43 319C84 368 110 383 121 383C126 383 128 382 128 377C128 370 127 359 122 343C99 268 84 204 77 156C74 137 70 111 70 104C70 25 125 -12 180 -12C228 -12 276 12 319 50C338 8 378 -12 418 -12C549 -12 689 166 689 332Z" id="g113-120"></path></g></svg> for different bit length.

Security and Communication Networks

tab4

Table 4

Table 4: Utilizing the Double-Precision Floating-Point Computing Power of GPUs for RSA Acceleration 