Research Article
An Efficient High-Throughput and Low-Latency SYN Flood Defender for High-Speed Networks
Table 2
Synthesis results for the proposed SYN flood defender core implemented in the NetFPGA 10G platform.
| Hardware resources usage |
| Resources | SYN flood Def. | OpenFlow |
| Register | 4,435 | 80,080 | (2.96) | (53.47) |
| LUT | 4,411 | 70,825 | (2,95) | (47.29) |
| BlockRAM | 18 | 200 | (5.56) | (61.73) |
| Frequency and Power consumption |
| Maximum frequency | 100.503MHz | 100.908MHz |
| Power | 11.756W | 12.040W |
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