Adaptation of MPDATA Heterogeneous Stencil Computation to Intel Xeon Phi Coprocessor

Table 1

Specification of tested platforms [36].

	First platform		Second platform
Product	Intel Xeon	Intel Xeon	Intel Xeon	Intel Xeon
	E5-2697 v2	Phi 3120A	E5-2665	Phi 7120P
Code name	Ivy; Bridge	Knights; Corner	Sandy; Bridge-EP	Knights; Corner
Number of cores	2 12	57	2 8	61
Number of threads	2 24	228	2 16	244
SIMD length [bits]	256	512	256	512
Freq. [GHz]	2.7	1.1	2.4	1.238
Peak [GFlop/s]	518	1003	307	1208
LLC size [MB]	2 30	28.5	2 20	30.5
Memory size [GB]	64	6	64	16
Memory bandwidth [GB/s]	2 51.2	240	2 51.2	352

Last level cache (LLC) refers to L3 cache for CPU, and to L2 cache for Intel MIC.