Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips

<table class="figure-group"><tr class="fig-image" id="a"><td><object data="https://static.hindawi.com/articles/sp/volume-2015/937694/figures/937694.fig.0015a.svgz" name="937694.fig.0015a" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(a) </b>P-1 implementation</td></tr><tr class="fig-image" id="b"><td><object data="https://static.hindawi.com/articles/sp/volume-2015/937694/figures/937694.fig.0015b.svgz" name="937694.fig.0015b" type="image/svg+xml"></object></td></tr><tr class="fig-caption"><td><b>(b) </b>P-2 implementation</td></tr></table>

<div>Run time comparisons for<b> Dict_Input_S</b>: (a) P-1 implementation; (b) P-2 implementation.</div>

Scientific Programming

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Figure 15

Figure 15: Cache Locality-Centric Parallel String Matching on Many-Core Accelerator Chips 