Scientific Programming

Volume 2017, Article ID 8686971, 13 pages

https://doi.org/10.1155/2017/8686971

## Modeling the Power Variability of Core Speed Scaling on Homogeneous Multicore Systems

^{1}Department of Computer Science and Technology, Tsinghua University, Beijing, China^{2}School of Computing, Clemson University, Clemson, SC, USA^{3}Intel Corporation, Santa Clara, CA, USA^{4}School of Computational Science and Engineering, Georgia Institute of Technology, Atlanta, GA, USA^{5}Department of Computer Science, University of Warwick, Coventry, UK

Correspondence should be addressed to Zhihui Du; nc.ude.auhgnist@hzud

Received 10 June 2017; Accepted 18 September 2017; Published 25 October 2017

Academic Editor: Thomas Leich

Copyright © 2017 Zhihui Du et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### Abstract

We describe a family of power models that can capture the nonuniform power effects of speed scaling among homogeneous cores on multicore processors. These models depart from traditional ones, which assume that individual cores contribute to power consumption as independent entities. In our approach, we remove this independence assumption and employ statistical variables of core speed (average speed and the dispersion of the core speeds) to capture the comprehensive heterogeneous impact of subtle interactions among the underlying hardware. We systematically explore the model family, deriving basic and refined models that give progressively better fits, and analyze them in detail. The proposed methodology provides an easy way to build power models to reflect the realistic workings of current multicore processors more accurately. Moreover, unlike the existing lower-level power models that require knowledge of microarchitectural details of the CPU cores and the last level cache to capture core interdependency, ours are easier to use and scalable to emerging and future multicore architectures with more cores. These attributes make the models particularly useful to system users or algorithm designers who need a quick way to estimate power consumption. We evaluate the family of models on contemporary x86 multicore processors using the SPEC2006 benchmarks. Our best model yields an average predicted error as low as 5%.

#### 1. Introduction

We consider the problem of how to model the power of a modern multicore processor as a function of the speed of its cores. On its surface, the problem seems simple as it is natural to assume that cores are independent of one another: the classic power model posits that the total processor power is the sum over that of independent cores. However, we find that in practice such modeling methods do not adequately capture what happens on real multicore systems in which there may be interactions among cores.

By way of motivation, let us consider the following classic model and then compare what it predicts to what happens in an actual experiment. In the classic single-core model, the power, , consumed by a core is expressed as the following function of its operating frequency (“speed”), :where is a workload-dependent factor and is a hardware technology-dependent parameter. For simplicity, (1) omits a term for constant (or static) power, but our argument and methods hold with or without the term. This model appears in a variety of papers on the power-aware scheduling problem [1, 2], in particular when the system provides dynamic voltage and frequency scaling (DVFS) [3, 4].

A widely adopted approach used for multicore power modeling extends from the method for single-core power modeling. It sums the power consumed by individual cores [5–8]. As a result, the power consumption of an -core processor, denoted by , is calculated by Critically, this approach assumes* independence*: the power of an individual core does not depend on what is happening on other cores on the same chip. Consider an environment consisting of multiple homogeneous cores, where all cores execute the same workload. In this setting, one may derive two predictions from (2). First, all cores contribute to the total power consumption independently. Second, scaling any core from one speed to another causes the same change in the total power consumption, regardless of the speed of the other cores. In other words, the cores have uniform power effects with speed scaling. For example, suppose a multicore processor has 16 cores with their frequencies set as . If , then changing the frequency of core from to causes a total power change of , which will have the same value as if we change the frequency of core from to .

However, the observations made in our experiments contradict these predictions. Figure 1 shows how the total processor power varies with a sequence of frequency scaling on a representative homogeneous multicore processor. In our experiments, all cores execute the same workload. The experimental results may be summarized as follows.(i)The effect on power from speed-scaling a core* depends* on the states of the other cores. The resulting change in total power depends on whether the scaling updates the maximum speed among the cores. This observation contradicts the first prediction derived from (2).(ii)The scaling that updates the maximum speed among the cores leads to a significantly larger change in total power than others. That is, the same increase in speed among the cores may have nonuniform power effects. This observation contradicts the second prediction derived from (2).