Research Article
SEDC-Based Hardware-Level Fault Tolerance and Fault Secure Checker Design for Big Data and Cloud Computing
Table 2
Results of single faults on FS SEDC1 checker.
| | G0 | S0 | V1 | V0 | G0 | S0 | V1 | V0 | G0 | S0 | V1 | V0 |
| | MOS P1or P2 is stuck ON | MOS P1 or P2 is stuck OFF | Input C0 stuck at zero |
| | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | ★0 | 0 | 1 | 1 |
| | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 |
| | MOS P3 or P4 is stuck ON | MOS P3 or P4 is stuck OFF | Input F0 stuck at zero |
| | 0 | 1 | 1 | 0 | 0 | 1 | Floating | 0 | ★0 | 0 | 1 | 1 |
| | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 |
| | Transistor N1 is stuck ON | Transistor N1 is stuck OFF | Input C0 stuck at 1 |
| | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 |
| | 1 | 0 | 1 | 0 | ★1 | 0 | 1 | 1 | ★1 | 1 | 0 | 0 |
| | Transistor N2 is stuck ON | Transistor N2 is stuck OFF | Input F0 stuck at 1 |
| | 0 | 1 | 1 | 0 | ★0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
| | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | ★1 | 1 | 0 | 0 |
| | Transistor N3 is stuck ON | Transistor N3 is stuck OFF | - | - | - | - |
| | ★0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | - | - | - | - |
| | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | - | - | - | - |
| | Transistor N4 is stuck ON | Transistor N4 is stuck OFF | - | - | - | - |
| | ★0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | - | - | - | - |
| | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | - | - | - | - |
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★The cases where circuit shows self-testing property.
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