First Steps in Porting the LFRic Weather and Climate Model to the FPGAs of the EuroExa Architecture

Table 1

Performance and utilization metrics from the Vivado HLS synthesis report for the double-precision matrix-vector code for a range of target clock periods.

Target clock (ns)	Estimated clock (ns)	Latency (clocks)	DSP48E total	DSP48E dadd	DSP48E dmul	FF	LUT
100	87.50	2306	42	3	11	28960	9023
50	43.75	2306	42	3	11	28960	9023
20	17.50	2312	14	3	11	20423	6751
10	8.75	2315	14	3	11	20742	6889
5	4.99	2321	14	3	11	21466	6860
2	2.89	2334	10	0	10	23199	7203
1	1.96	2336	10	0	10	23570	7200
0.5	1.96	2336	10	0	10	23570	7200